A Hardware Acceleration Of Image Classification Algorithm Based On Convolutional Neural Network Implemented On FPGA

Convolutional neural networks(CNNs)have made a great contribution to the research of computer vision and pattern recognition,because of their high performance.As a result,CNNs have become a hot topic in the field of computer science.However,the requirements of the computing power and power consumption on portable devices make it difficult to complete the work of CNNs by using graphics processing units,and web services are often required as an alternative.In order to reduce the cost and power consumption on portable devices by using the Application Specific Integrated Circuit(ASIC)in the future,A hybrid CNNs structure implemented on fieldprogrammable gate array(FPGA)is proposed to reduce multiplicative calculation under the premise of ensuring the accuracy.The work of this paper mainly includes the following three points.Firstly,for the complex multiplication of the convolutional layer,the floating-point multiplication in the convolutional layer is transformed into a simple XNOR operation by quantization to save the resources of multiplier and reduce the complexity of calculations,and the original fully connected layer structure is preserved to guarantee the accuracy of model recognition.Secondly,due to the characteristics of receptive fields in CNNs,an inter-layer pipeline structure is designed to play the parallel computing ability of hardware circuit.Thirdly,a natural storage strategy is proposed to reduce the time cost in data access and facilitate the calculation.Combining the above three points,an accelerator for Lenet-5 is deployed on the platform of Xilinx Artix-7 xc7z020clg400-1 in this paper.The result shows that the accelerator can classify each picture from MNIST in 18.97 at the clock frequency of 150 MHz,with 0.4% loss of recognition accuracy and 85.6% reduction of multiplication.