Image Segmentation Neural Network Design And Hardware Implementation For Artificial Visual Prosthesis

Visual disability is one of the most serious diseases affecting human life.Studying artificial vision prostheses can give blind people hope to regain their vision.Image processing is a core component of artificial vision prosthesis system.This paper studies the application of image segmentation neural network design based on deep learning and FPGA-based hardware acceleration design on artificial visual prosthesis.Based on the indoor scene,this paper selects eight types of objects,such as beds and sofas,which are commonly used indoors,and produces 256*256 RGB image data sets.In the design of image segmentation network,the full convolutional neural network is improved and applied to artificial vision prosthesis for the problems of high hardware cost and long running time.Change the filling unit of the first convolution layer from 100 to 1,change the size of the first convolutional layer convolution kernel to 3*3,and change the number of channels in the full convolution layer to 1024.The adjustment also halved the convolution kernel and the step size of the last deconvolution layer to obtain a network of different output size segmentation images.The improved segmentation network and the original segmentation network were trained on the K80 GPU server,and the performance of each network was statistically compared.The results show that the improved segmentation network has a faster segmentation speed and a smaller hardware cost than the original segmentation network.Among them,the memory usage is reduced by more than 3 times,the model size is reduced by more than 6 times,and the running time is also increased by more than 3 times,and the drop of about one percentage point in the segmentation accuracy is acceptable for visual prosthesis applications.This paper completed the design and verification of hardware accelerated IP for improved full convolutional neural network algorithm.The architecture design of IP and the design scheme of each module are elaborated.The RTL design of IP is completed by Verilog language,and it is packaged by axi4 bus protocol.A simple control instruction system is also designed for IP hardware and software interface.control.In addition,since the visual prosthesis studied in this paper is based on the 32*32 microelectrode array,the function of processing the improved segmentation network segmentation into 32*32 size is also designed.In this paper,after the implementation of the Modelsim-based functional simulation and the Matlab-based computational model for collaborative verification,the VC709 FPGA development kit is used for hardware implementation verification.The verification results show that the design clock can reach 135MHz,and the processing speed of the FPGA is estimated to be 1.5 times that of the Xeon E5-2620V4 CPU on the server,and the power consumption of the FPGA is only 4.8%of the server CPU.Image segmentation has a wide range of application scenarios.The design of this paper has reference significance for dealing with other image segmentation tasks(such as medical image segmentation).The shortcoming of the design is that real-time performance needs to be improved.