Design And Implementation Of Target Detection System Based On Heterogeneous Computing Platform

Today's convolutional neural network has achieved great success in the field of target detection,but most of the implementation environment is on the GPU-CPU computer architecture.However,GPU power consumption is not suitable for embedded devices and the CPU cannot perform large-scale parallel computing.Because FPGA has the low power consumption and it is reconfigurable,it can solve the above problems.Therefore,it is of great significance to design a target detection system based on the FPGA-CPU architecture.This article designs a target detection system based on Xilinx's Zedboard,which is based on the FPGA-CPU architecture and the two parts can communicate through the AXI bus.Because the CPU is suitable for processing tasks with a small amount of calculation,it is mainly responsible for image pre-processing and image post-processing.FPGA is good at processing highly parallel and large-scale tasks.Therefore,this article mainly uses its parallelism and uses HLS to design multiple parallel multipliers and adders to optimize the convolution layer and pooling layer of the Tiny-YOLOv2 algorithm.Because FPGA is not good at processing floating point data,16-bit fixed-point data is used instead of floating-point data.In order to improve the detection speed,the BN operation is advanced to the initialization module.The construction of the hardware image processing channel mainly uses the stream processing method based on the AXI bus to save the FPGA's on-chip resource Block RAM,and transfers the picture data captured by the OV7670 to the DDR in the PS terminal for storage.After the algorithm recognition,the VGA is output to the screen on.The experimental results show that the system has basically achieved the expected function: after the camera captures the image through the coarse-grained extraction process of the FPGA,the corresponding target is detected,and the VGA output is displayed on the screen.The FPGA-CPU heterogeneous architecture used in this design has more than 80 times improvement in latency compared to the single CPU architecture;although the FPGA is not as powerful as the GPU,the energy efficiency ratio is better than FPGA,which is suitable for deployment in specific power consumption embedded fields.In addition,although this article has adopted quantitative processing,it can still output the position coordinates close to the original algorithm detection frame,which can be put into engineering practice.