Cluster Based Architecture Synthesis Minimizing The Resources Under Time Constraint

With the increased hardware circuit complexity, high level synthesis plays animportant role in the whole design process. For digital signal processing (DSP)applications, high performance using minimal resources has become a serious problem.The number of addressable registers is a significant obstacle for centralized architectureachieving high performance of DSP applications. In clustered architecture, register fileand function units are all partitioned into clusters so that short CPU cycle time and moreregisters can be offered.In this paper, we give the architecture mode, data flow mode and time mode byconsidering different factors. Based on these modes, we propose a novel homogenouscluster based architecture synthesis framework using minimal resources under time andregister constraints, which substitutes adding a cluster for inserting memory operationswhen registers are inadequate. By counting the register, inter-cluster communicationsand function units requirements during scheduling, the cluster with optimal performanceis selected to schedule every instruction of the application. The cluster assignment,instruction scheduling and register allocation are integrated in a single phase during thescheduling. Furthermore, we propose an algorithm to optimize the redundant resourcesof initial configuration. Finally, we schedule the MOVE operation to minimize thenumber of communication. The experiments demonstrate that our approach compareswith the centralized architecture synthesis, achieving up to96%improvement in successrate for general cases and up to224%improvement for cases with tight constraints, andcan also effectively reduce the resources.