Construction Of A Platform For SOC Performance Evaluation

The development of the chip has evolved from the most primitive single-performance singlechip ASIC to a So C system carrying a processor,a memory,an IP module and a bus,and then to a complex system of a multi-core multi-level bus.Although the performance has been improved,the huge design scale and complex architecture make So C system-level software and hardware architecture design and development face huge challenges.Relying on traditional RTL simulation alone cannot keep up with the pace of development.Therefore,research based on electronic system-level evaluation systems to quickly evaluate the performance of So C systems through high-level modeling is quietly emerging.The system-level evaluation system is of great guiding significance and practical reference value for the initial design of the system-on-chip architecture.This paper proposes a construction method for So C performance evaluation platform.The main work is as follows:This dissertation takes the highly flexible and versatile So C processor performance modeling technology as the starting point of design,combines dynamic simulation and static analysis technology,and evaluates the application program on the corresponding processor of the So C according to the software task division method and the software-hardware mapping relationship.Computing load.It is used to solve the problem of poor versatility of So C software and hardware system performance evaluation technology caused by the diversification of SoC processor architecture.During the design process,the processor behavior model is first established;secondly,the processor power consumption probability distribution model is studied to establish the mapping relationship between instructions and power consumption;then,the mapping mechanism of software code and instruction system is constructed,and the original simulation technology is used Evaluate the target instruction execution coverage rate;finally,comprehensively evaluate the processor calculation cycle,memory data access amount,etc.in combination with the application program instruction distribution and instruction execution cycle weight.This dissertation is based on the efficient and flexible So C multi-level memory architecture modeling technology,and focuses on the research of cache modeling architecture,indexing mechanism,and state update strategy.It solves the problems of low evaluation efficiency and poor versatility caused by many types of So C storage model structures,slow simulation speed,and poor configuration.In terms of architecture characteristics,in view of the flexible,diverse,and complex synchronization characteristics of the So C cache architecture,this dissertation uses a hierarchical cache architecture model.In terms of the indexing mechanism,the program instruction,data block status,and cache block status models are established to record the program instruction block's mapping status in caches at all levels and cache block-like labels,replacement strategies,and synchronization bits,so as to achieve constant time hit detection mechanism.The system and network-based TLM modeling method is used to model the peripherals and bus.With the rapid modeling environment of OVP,a complete So C system is built,and the corresponding test software system program is written to verify,and finally the architecture performance of the So C system is obtained,mainly including the computing power of the processor,the hit rate of the cache model,and the communication rate and accuracy of the peripherals and other indicators.The situation has certain guiding significance and value for the initial design of the SoC system.