Research And Implementation Of Software And Hardware Codesign Of Convolutional Neural Network Based On ZYNQ

As the core algorithm in the field of deep learning,convolutional neural network combines feature extraction and classification.Compared with manual feature extraction and classification,convolutional neural network has higher detection accuracy.Because of its complex network structure,each layer contains a large number of parallel multiplication and addition operations,the hardware platform needs to have a strong parallel computing capability.FPGA,as a programmable logic device,has the advantages of high parallelism and programmability,and can be used for parallel acceleration of different algorithms.Therefore,it becomes an important choice for implementing convolutional neural network.In this paper,the hardware acceleration of convolutional neural network is studied based on the ZYNQ chip of Xilinx company.This paper analyzes the structural characteristics of convolutional neural network,and gives full play to the advantages of ARM and FPGA by means of hardware and software co-design,The port of Linux operating system and the design of hardware and software coprogram are completed by ARM.FPGA terminal realizes the design of convolution computing module,depth separable convolution computing module,pooling computing module,data input and output module.In view of the long broadcast and multi-fan in and multi-fan out data path problem caused by parallel expansion,this paper adopts systolic array instead of parallel expansion,converts the long distance data path into the short distance data path between each processing unit,and completes the design of convolution computing module.In the way of data transmission,the method of multi-channel data transmission and intermediate cache is adopted to reduce the time of data transmission between DDR memory and on-chip cache,and the design of data input and output modules is completed.In the aspect of hardware IP optimization,each module is executed by pingpong streamline operation to increase the efficiency of each module and reduce the overall running time of hardware IP.Fixed point quantization of floating point data to reduce the use of on-chip storage resources.To solve the problem that the storage resource on FPGA chip cannot store all the weighted parameters and intermediate data,the convolutional neural network is divided into blocks,and the hardware structure is optimized by Roofline performance evaluation model to meet the hardware resource limitations.The overall design of the hardware IP of convolutional neural network is accomplished by using Vivado HLS high-level comprehensive tool.In the experiment,Zedboard development board was used to evaluate the co-design of software and hardware through two convolutional neural networks with different structures.The results show that the hardware acceleration of the convolutional neural network is realized by using the ZYNQ chip in the way of hardware and software co-design,which has the advantages of good acceleration effect and low system power consumption under the condition that the detection accuracy is basically consistent with that of floating point data types.