Chip Design Of Convolutional Neural Networks Algorithm Based On Reconfigurable Computing Platform

Convolutional Neural Networks(CNN)has been widely used in the fields of image recognition,target detection and speech recognition with the rapid development of deep learning,due to its high accuracy in data classification.Because convolution and fullyconnected layers that are compute-memory-intensive,it is difficult to perform real-time classification on existing CPUs and GPUs.Taking into account high performance and versatility,reconfigurable computing systems can support multiple neural network training and inference operations through configuration and reconstruction.Based on a reconfigurable intelligent accelerated nuclear platform,this paper completes the inferring process of CNN,and accomplishes the following two tasks:Firstly,it explores the design of the CNN algorithm based on the systolic-like array architecture(Machine learning Unit Array,MU Array),and periodic accurate system simulation model is established by System C language.Through the analysis of the simulation results,the computational delay is significantly lower than that of the similar accelerators using the addition tree.Secondly,accomplishing the hardware implementation of the CNN algorithm based on the MU array.The convolution layer,the pooling layer and the fully-connected layer compute as the separate operator.In convolution calculation,the MU array can support the parallel calculation of 32.In addition,some computational time and memory access time can be masked by ping-pong operation,which can improve the efficiency of calculation.Based on the Alex Net network model,simulation verification and synthesis of the algorithm.The effective throughput rate of this design can reach 1.85 TOPS,and the resource utilization rate can reach 92.43%.