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Design And Implementation Of Convolutional Neural Network Acceleration Based On ZYNQ

Posted on:2022-05-10Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y DaiFull Text:PDF
GTID:2518306509956129Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
As an outstanding algorithm in the field of deep learning,convolutional neural network has attracted more and more attention from researchers.It has excellent performance in image classification,speech recognition,object detection and natural language processing,etc.However,the very large amount of parameters and calculations of convolutional neural networks have brought considerable pressure to the hardware platform.With its advantages of highly parallel computation,repeatable programming and low power consumption,FPGA has become a hot topic in the research of hardware accelerated convolutional neural network.This paper has completed the accelerated design of convolutional neural network based on ZYNQXC7Z020 platform.The ZYNQ chip integrates ARM processor and FPGA,which is suitable for the co-development of embedded system hardware and software.In this paper,the main work is as follows: first,the specific hardware acceleration network is determined as YOLOV3-Tiny,the structure and parameter characteristics of the network are analyzed and the quantization method of network data is determined to be 16-bit fixed-point quantization.A variety of convolutional neural network acceleration schemes on FPGA hardware platform are studied and analyzed.Finally,a more reasonable hybrid parallel acceleration strategy is developed based on the characteristics of Yolov3-Tiny network and the hardware resources of ZYNQXC7Z020 platform.Then the storage arrangement of network parameters is optimized and the mobile strategy of network data on ZYNQ is formulated.Based on the data mobile strategy and parallel acceleration strategy,the accelerated IP core is designed and packaged in Vivado HLS.Finally,the hardware and software design of the system is completed in Vivado IDE and Xilinx SDK,and the acceleration of Yolov3-Tiny network by ZYNQ platform is realized.The experimental results are analyzed and compared with other hardware platforms.In the experiment,the throughput of ZYNQ-XC7Z020 platform reached9.12 GOPS,and its computing performance was 228 times that of the ARM Cortex-A9 processor and 11 times that of the Intel i5-9300 h CPU.The platform consumed 79%DSP resources and 66% BRAM resources,and the total hardware power consumption of the system was 2.141 W,which met the ZYNQ platform's acceleration design requirements for Yolov3-Tiny network with low power consumption and high performance.
Keywords/Search Tags:ZYNQ, convolutional neural network, hardware acceleration, YOLOv3-Tiny, parallel computing
PDF Full Text Request
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