Neural Network Algorithm FPGA Implementation And Performance Optimization

In the field of artificial intelligence,most of the neural network computing tasks are currently completed by CPU and GPU.The traditional chip computing architecture can no longer support the massive parallel computing requirements of neural networks,which requires new underlying hardware to better accelerate the calculation process and provides computing power for the realization of the entire artificial intelligence.FPGA is very suitable for improving the computing performance of neural networks based on its excellent reconfigurability and parallel computing characteristics.Therefore,it is of great practical significance to study the neural network computing architecture based on FPGA.In this paper,by analyzing the characteristics of neural network computing and the hardware characteristics of FPGA chips,this paper summarizes several key issues that need to be studied in the process of FPGA implementation of neural networks,and gives the optimized design plan.The main research contents include:(1)Several fitting methods of typical activation functions are discussed.On the basis of comparative analysis,an optimal equidistant piecewise approximation method is proposed to linearly fit the activation functions and improve the fitting accuracy;(2)By comparing the prediction error of the neural network under different fixed-point digit combinations,the relationship between the fixed-point digit and the error is obtained,and the preferred value of the fixed-point digit is determined accordingly;(3)The adaptability,application potential and limitation of the two kinds of operation mode of systolic array are analyzed when applying this operation mode to the multiplication and addition operation of the neural network;(4)Because CSD coding can greatly reduce the partial product generated during the multiplication operation,therefore,a reloadable coefficient multiplication module based on CSD coding is designed,which not only reduces the resources occupied by the multiplication operation,but also reduces the number of gate flips during the operation.Based on the research of the above key technologies,a hardware architecture of a systolic array neural network suitable for parallel operation is proposed.This structure further improves the systolic array according to the operation needs of the neural network,ensuring that the operation has deep pipeline characteristics and simplifying the operation process control;more importantly,the architecture makes the single-layer neural network structure reusable,greatly reducing the consumption of chip resources.Finally,this neural network design method is applied to the simulation model of PID control.Through simulation,it is found that the neural network control algorithm based on FPGA meets the predetermined control requirements,which proves the feasibility of the method described in this article.