Design Of Digital Receiver Synchroization System And Implementation Of FPGA

With the development of communication systems and the carrier frequency of transmission is getting higher,and the position occupied by digital receivers in communication systems is becoming more and more important.In the communication system,since the signal is affected by channel skew,multipath interference,doppler effect,etc.There is a certain deviation between the signal received by the receiver and the transmitted signal,if the deviation is coherent demodulation can't be eliminated in the process,will affect the signal quality of the communication or cause the interruption of the communication system.Therefore,in the digital communication system,the received signal needs to be synchronously processed to ensure that the coherent carrier and the synchronous clock can be generated in the digital receiver,and the original signal can be accurately recovered and demodulated.The function of the synchronization system in the digital receiver is mainly to ensure the accuracy of the digital receiver in coherent demodulation and the consistency of symbol symbols,and to ensure the communication system of the correct operation.So the synchronization system is indispensable for digital receivers in the digital communication process.This paper focuses on the synchronization system design and FPGA implementation of digital receivers.In the design of digital receiver synchronization system,the two algorithms of carrier synchronization and symbol synchronization in the synchronization system are analyzed firstly,and the working principle and design idea of each main module in the synchronization system are emphasized.Determine the design parameters in the synchronous system,and use Matlab software to verify the algorithm.In the Vivado 2015.4 integrated development environment,the synchronous system Verilog HDL program is written,and the simulation verification of the synchronous system is performed under the Modelsim software.In the digital receiver hardware design and implementation,the design of the digital-to-analog conversion module uses the AD9628 chip to convert the intermediate frequency analog signal into a digital signal.Digital receiver hardware platform based on FPGA implementation,The design of the hardware platform includes a power module,a clock module,an FPGA module,and an ADC module.Finally,the digital receiver synchronization system is tested online on the hardware platform.The test results show that the test condition is 80 MHz,the signal bandwidth is 5MHz,and the signal center frequency is 5MHz.In the synchronous system,the carrier synchronization is within the range of ±50KHz,the acquisition accuracy is ±10Hz,and the symbol synchronization can realize the correctness of the output binary symbols.