Hardware Implementation Of Data Processing Algorithm For Ptical Analog-to-digital Conversion System

Analog-to-digital conversion (ADC) is the key component of dataacquisition systems. It converts the analog signals to digital signalswhich is much easier to be stored and processed. With the developmentof the electronic technology, the sampling bandwidth and the effectivenumber of bits, known as ENOB, have been experienced increasinglydevelopment in terms of performance. But the electrical clock jitter hasalways been an obstacle for ADC convertors to sample wide-band signalswithout losses at a high rate. So it cannot meet the increasing demand forwide-band applications in communications. Photonic Analog-to-digitalconversion is well known for its wide-band, high-precision, low-jitter andhigh-stability. Signal processing with the help of photonic technologycan overcome the clock jitter brought by EADC, improving theperformance of analog-to-digital conversion. PADC is an effective wayto enhance the performance of sampling rate and ENOB, proving itself abroad application prospect.There exist inconsistencies among channels of the OADC system andnon-linearity generated from sampling the signals. For this reason, aparticular algorithm for correction and reconstruction of the signals shouldbe applied in the system. Errors are somehow inevitable during thesampling process, some of which are magnificent. So applied withcorrection and reconstruction technologies, the OADC systems are able to get rid of the redundancies and errors brought by the sampling stage andrebuild the signals to ensure their validity. In this thesis, principles arefirstly given to prove the correctness of the correction and reconstructiontechnologies. And then FPGA based implementation is carried out bothin simulation and in realization. Transmission and visualization of thedata are also completed to make the end part of the OADC system as awhole.Firstly of the thesis, a deep analysis is given to the cause of theinconsistencies of the multiple channels, which goes to the importance ofthe correction and reconstruction algorithm. And the current situation ofthese algorithms and technologies are pulled out for discussion andcomparison. After that, the principle and advantage of the algorithm thatis applied in our system is laid out in details.Secondly, the framework of the end part of the OADC system and itsdesign are presented, including the framework of the realization of thealgorithm, correction and reconstruction for dual-port and multi-portchannels as well as the data transmission from FPGA to PC and the datavisualization.Thirdly, with the assistance of System Generator as the middleware,the implementation of the algorithm on FPGA is then completed and tested.A profound analysis is made for the working process and the principles ofsuch design. Mufti-port FPGA based implementation of the algorithm isthen presented its logic process and design schematic, on top of the workdone for the dual-port algorithm.Finally, communication is established between the FPGA and the PCwith PCI as the interface to testify the data transmission and the precision of the applied algorithm. A user interface is brought in to monitor thereal-time data. Results show that the average mean error is less than1%for the FPGA based implementation, achieving the requirements of theOADC system. Therefore the feasibility and practicality is proved for theFPGA based implementation of the correction and reconstructionalgorithm.