Test And Improve Of Verilog/VHDL To MSVL Converter

With the development of computer,hardware systems have gradually penetrated into various fields,providing convenience for people's lives.However,the structure of the hardware system is gradually more complicated,and a small mistake may lead to the collapse of the system.It is especially important to verify the correctness of the hardware system.This paper tests the function of Verilog/VHDL to MSVL converter,and solves the problems in the converter according to the test results.The specific work includes the combination of Verilog to MSVL converter and VHDL to MSVL converter into V2 M.When the problems occur,corresponding improvement schemes are proposed and implemented in full.The V2 M converter in this paper is implemented using an automated classification method.The V2 M converter uses different sub-converters to convert source files according to different classification results,which improves the practicability of V2 M converter.And adaptive optimization of V2 M converter based on MSVL syntax change is implemented during the merge process.The V2 M converter is then dynamically tested by unit test,integration test,white box test,black box test,etc.,and the code specification of the V2 M converter is statically tested using the C++ Test tool.The test results reflect that the V2 M converter has problems in handling the partial statement structure and the code is not standardized.The paper then improves the V2 M converter to solve the above problems.Firstly,the process of dealing with the trinocular operator operation by the converter is improved,and the problems in the conversion assignment operation and the exclusive OR operation are solved.Then the converter code is normalized according to the MISRA C++ 2008 rules.This paper has solved eight dynamic test problems of V2 M converters and more than one thousand static violations.By comparing the V2 M converters before and after the improvement,the test results show that the improved V2 M converter has more complete functions,better logic coverage and code specification.