A System Translating VHDL Into MSVL

Very-High-Speed integrated circuit hardware description language(VHDL) is a kind of advanced computer language used to design circuit,which describes logic function,struct of circuit and connection form of electronic system in software programming method.Although VHDL has been instead of by Verilog,it is also applied in many fields for its portability,strong expression ablity,fast development speed and independence.Because of the continuous expansion of software’s scale and application in aerospace and military.It is necessary to check the correction of program.modeling,simulation and verification language(MSVL) is a kind of interval temporal logic language which is used for simulating,modeling,verification.for eliminating logic error,BUG and other hidden danger in VHDL programming,we develop a translation program. The MSVL file is equal to VHDL file in logic and semantic.Put MSVL file into MSV interpreter to execute,we can simulate and verify the VHDL source code.This paper discusses about the method of programming language translation,which is consists of several parts below:1.Research on compile principle.according to demands,I studied some technology like nondeterministic finite automata,deterministic finite automata,analysis from bottom to top,lexical analyzer and syntax analyzer.The translation ftom VHDL to MSVL is based on these technology.To make translation successful,I made a series of translation rules.2.Research on generation of lexical generator and syntax generator.lexical analyzer and syntax analyzer are important parts in translation system,which are also the basis of translation.Lexical analyzer can be built by lexical generator,like Lex.Before lexical analyzer generated,the regular expression and user code should be coded.These regular expressions are used to identify the token in source code.When a expression is matched,user code will be executed.Syntax analyzer can be built by syntax generator,like Bison.The Major work is the coding of production and user code,which is similar with the code of lexical analyzer. That could reduce development time.3.Research on syntax structure about VHDL and MSVL. This software makes a pretreatment on VHDL source code with lexical analysis and syntax analysis. System stores the information which is from production when syntax analysis. As a result of that,syntax tree,symbol table,sub program collection,entity collection and package collection is produced.The root of syntax tree will be given to translation program after syntax analysis. Translation program will run in the following order. firstly,the content in package collection will be translated.On that package translation is finished,sub-program is processed.second,non-top level entity should be handled.lastly,top level entity could be translated.Apart from the above,the result string should be written into output file.If translation program finds error or exception in the process of translation,program will output error information and exit directly.4.Research on an instance of a VHDL program.The instance is about the universal asynchronous receiver/transmitter,which is a peripheral of LEON3 processor system. According to research,the correctness of program could be ensured with the translation program from VHDL to MSVL designed by us,which is benefit to promote the reliability of software as while as to provide a new idea to test program.