Key Problems On Transforming Verilog Into MSVL Programs

Verilog has a simple editing environment and a variety of design methods. It can either be used to not only describe the structure and behavior of hardware system model, but also the function of the system. It has been widely used in designing digital circuit system with simple and diverse forms. The diversity of requirments and functions makes the complexity of hardware system increase; the correctness of hardware system design seems more and more important. Currently, some software simulation, hardware emulation, software and hardware co-simulation tools extent the analysis and evaluation of the model of hardware system, but they are complex in use, expensive, and have great limitations.In formal verification, as a powerful theoretical tool, temporal logic is more and more widely used in the design of hardware and software system. Based on temporal logic theory, a series of tools have been developed, such that modeling, simulation and verification can be done through these tools.Modeling Simulation and Verification Language is a framed temporal logic programming language. It is popular with compactness, highly efficient operation and simple simulation environment. In the case that verilog programs are converted to MSVL programs, simulation, model checking, verification can be carried on to detect errors in the original Verilog program, this is useful in ensuring the correctness of the system design.This thesis studies and solves several key problems in the transformation process from Verilog to MSVL: nested relations mapping, prepared statements transformation, analog of hardware timing characteristics, interface mapping and management of variables. First, it describes the syntax rules and semantic features of MSVL and Verilog languages, and gives the basis to convert the two languages. Then it elaborates the architecture of transformation tool and key problems to be solved. Finally, the plan to build real-time simulation environment for MSVL is proposed and realized. Meanwhile, some examples of Verilog are converted to MSVL programs; the results of real-time simulation of MSVL programs on MSV interpreter are given.Through functional tests for software from Verilog to MSVL, it is shown that the key problems in the transformation process from Verilog to MSVL have been resolved, and the desired objectives are achieved.