Research And Implementation Of Frequency Synthesizer With Multi-interface Level Output

With the continuous development of communication technology and deep space detection technology,better and better requirements are placed on the performance of frequency sources.Especially for the 5G communications currently being developed vigorously in the world,compared with the previous generation of communication technology,the rate is increased by 100 times,and the delay is reduced by 30 to 50 times.This requires a frequency synthesizer for scientific research and measurement of high-performance systems,the synthesizer has an extremely high accuracy,extremely low phase noise,and extremely short rise time.The rapid development of integrated circuits has promoted the diversification of chip functions and interface levels.It also puts forward corresponding requirements for the interface of measurement equipment.In order to meet the increasing testing requirements,a multi-interface level output,low phase noise,low-spur frequency synthesizer is imperative.The thesis conducts research and design on the frequency synthesizer with multi-interface level output,introduces the original and basic structure of PLL frequency synthesis technology,DDS frequency synthesis technology and DDS + PLL frequency synthesis,and analyzes the respective phase noise and spurs.The design scheme of frequency synthesizer with multiinterface level output based on decimal phase-locked loop is proposed.The key technologies such as high frequency resolution,integer boundary spurs caused by the fractional frequency division ratio,time modulation and high resolution phase setting involved in the scheme were investigated and proved to be effective.Completed the hardware circuit and logic control program design of frequency synthesizer with multi-interface level output.The hardware circuit includes frequency synthesis module,output interface level module and sequential logic control module.Among them,the multi-interface level output module includes LVDS output module,RS485 Output module,CMOS output module,PRBS output module,trigger clock output module and delay line module;the logic control program includes the design of integer frequency divider,PRBS output and the control program of the main hardware.Finally,a test platform was built to test the frequency accuracy,phase noise,rise time,fall time,and level values of the output signal of the designed frequency synthesizer.The test results verified the correct of the design.