Optimum Design Of AES Algorithms And Implementation On FPGA

With the current development of big data and various technologies of the network,information security has caused close attention in the field of communication.Satellite communications,microwave communications,and fiber-optic communications are the three pillars of today's communications arena.The focus of common research in these three fields is the protection of information in the process of communication.Information security is the most important part of the communication process.AES is a widely used data security technology in the field of communication.This thesis studies AES algorithm and optimizes its transformation.Firstly,after analysis and calculation,the new S-box cryptographic properties are used to improve the affine transformation period,the number of iteration cycles and the algebraic expression of the S-box.The cryptographic properties are better than the S-box of the original algorithm,and the security of the algorithm is improved.Secondly,the S-box is optimized.Since S-box is the only non-linear unit in the AES algorithm,S-box and inverse S-box need to be performed separately when performing encryption and decryption,especially in byte replacement.Two tables to operate,which will take up a lot of resources,this article makes the S-box and the inverse S-box share a table,that is,the previous two tables are merged.Then the original finite field is mapped to the composite domain for calculation.After the composite domain is calculated,it is mapped back from the composite domain to the finite field.This reduces the complexity of the multiplication inversion module and reduces the use area in the hardware implementation process.Reduce the complexity of the circuit.Thirdly,the column mixing algorithm reduces the computational complexity and improves the efficiency of the column mixing algorithm theoretically by changing the fixed polynomial.The optimization of the column mixing algorithm theory can be applied to the column mixing sub-module circuit.By adopting a new column mixing fixed polynomial,the logic used in the circuit is reduced.The number of devices and the complexity of the circuit.Fourthly,the AES hardware circuit with full pipeline structure is used in the design.In this way,not only the data encryption and decryption functions can be completed,but also the encryption and decryption can be carried out simultaneously.Using full pipeline can greatly improve the data throughput and clock frequency.In this design,three different key lengths can be chosen freely to encrypt and decrypt the data,which can meet the users' needs of different security levels.Verilog language is used to describe the whole algorithm,and Quartus tool provided by Altera Company is used to compile the AES algorithm.The whole module of the AES algorithm optimized in this thesis is simulated and verified with Modelsim simulation tool.The final simulation data show that the design can accurately complete the encryption and decryption of the AES algorithm,thus proving the overall correctness of the algorithm.