Research And Design Of AOT Controlled Built-in Dual Pll Buck DC-DC

The booming development of the electronic industry has brought tremendous vitality to the power management chip market.However,due to the higher integration,smarter and higher speed,the requirements for power chips are more stringent and diversified.Taking the buck DC-DC with the largest market share as the research object,around the characteristics of wide working frequency range,external clock synchronization,wide input voltage range,high efficiency and fast transient response,the research and design work of the chip XD1999 A is completed.By analyzing and comparing several common control modes,a better AOT control system is designed,which inherits the excellent features of COT valley current mode,such as simple,fast,stable,suitable for high frequency and small duty cycle operation,and by generating AOT timer to offset the influence of duty cycle,the working frequency is more concentrated.Studying the working frequency and the internal oscillator CLK wide range synchronous frequency lock implementation method,the on-time timer with adaptive regulation of input and output voltage,PLL synchronization adjustment,and automatic tracking of oscillator frequency is further designed,eliminating the effects of parasitism and delay in the circuit;The operating frequency and internal oscillator CLK can be quickly and strictly synchronized in the required frequency range,making the system EMI single,easy to handle,effectively reducing the performance requirements of the PLL,improving the transient load characteristics of the system,and making it convenient for applications of small volume inductors and capacitors at high frequencies.Studying the external frequency synchronization and wide range adjustment implementation method of working frequency,the external synchronization and frequency adjustment circuit of the chip is designed and optimized,and constitutes a dual PLL regulation system,which is convenient for chip frequency control and external synchronization applications.The key sub-module circuits of the chip including reference,internal LDO and ZCD are designed and analyzed;The internal LDO can convert the 3.6~20V input voltage into the internal 3.3V low-voltage source of the chip,meeting the wide range of input voltage requirements,and the combination of voltage type and current type Miller multiplying effect technology effectively reduces the area of internal compensation capacitor;ZCD is the key module in the BURST mode of the chip,the design of the fast comparator and the advance of the flip point are beneficial to further improve the efficiency.The circuit design of XD1999 A is carried out based on the 0.35?m BCD process.The performance of each module and chip is verified by Cadence's Spectre simulation tool.The results show that only 1.5p F compensation capacitor and 2.2?F output capacitor can make the internal LDO achieve a phase margin of not less than 65 degrees and a gain margin of 11.8d B in the full load range of 0~30m A,ensuring stability;The ZCD comparator delay is only 8ns,and the flip point is advanced by 8.9ns to offset the subsequent logic delay;The chip soft start is stable,the output voltage rises smoothly,and it can work normally in 0.5M~3.5MHz adjustable and 1.4M~2.6MHz external synchronous frequency range,and the working frequency is strictly synchronized with the internal oscillator CLK;In CCM mode,when the output capacitance is 100?F and the load step is 0~4A,the output voltage overshoot is only 56.1m V and the response time is only 24.8?s;The overall stability is good,the transient response speed is fast,the overshoot is small,and the peak efficiency can reach 95%,and all indicators meet the design requirements.