| Nowadays,with the development of modern microelectronics technology,electronic products are playing more and more important roles in life.Power Management Integrated Circuits(PMIC),as an important part of electronic products,is inseparable from the development of electronic technology.Buck circuit,as an important structure of DC-DC converter in PMIC,has attracted wide attention in recent years.With the continuous improvement of chip integration,the multi-phase Buck converter has a greater power density and a wider and more flexible application environment,which is now a research hotspot in the PMIC field.Due to the need to take it into account both for overall output characteristics of the converter and synchronization adjustment between the channels,and the affection between two feedback loops in the same converter system,the control principle of the multi-phase Buck is a challenge in research.For most cases in design,system synchronization control on the on-time adjustment is often limited within a small range of frequency,and the design criteria is often made to ensure the worst frequency stability,which limits the performance of the chip at other synchronization frequency points.At present,there are few mathematic models to describe the frequency synchronization adjustment of multi-phase Buck.The related design lacks theoretical guidance,so it is difficult to accurately design the bandwidth of the synchronization control loop.This paper uses the describe function method to conduct an in-depth theoretical analysis of the frequency synchronization control of the multi-phase Buck converter with PLL,and establishes an equivalent small signal model.According to the model,the design criteria for the frequency synchronization control of the multi-phase Buck are given.Based on the model and design criteria,this paper proposes an improvement plan for the control technology of adaptive frequency synchronization technology,which realizes the accurate design of the frequency synchronization PLL bandwidth in the multiphase Buck.This design enhances the stability of the system and at the same time improves the performance of the converter at each synchronous frequency operating point.This paper proposes a new PLL?COT control circuit architecture with dual-path compensation channel,which can easily realize the precise adjustment of the compensation zero position with frequency in the PLL?Buck system.In this way,adaptive frequency synchronization is realized,which greatly broadens the frequency synchronization control range of the multi-phase Buck converter.This paper will specifically introduce the circuit implementation method of the adaptive frequency synchronization improved PLL in the multi-phase Buck converter,as well as the innovative sub-module circuit blocks such as the zero compensation fast path block.Finally,based on the 0.18?m BCD(Biplor-CMOS-DMOS)process,this paper designs a PLL frequency synchronous valley current mode COT control 3A dual-channel Buck converter chip,and completes the self-adaptive frequency synchronization improvement according to theoretical analysis.The simulation verification of the overall system after the adaptive frequency improvement is completed by Simulink.And the Hspice simulation results of the chip show that the input voltage range of the chip can reach 3.6-20 V,the output voltage range can reach 0.6-5.5V,the maximum current of a single channel is 3A,and the general working efficiency can reach 90%.In particular,the input frequency synchronization range of the chip can be broadened to 1-10 MHz.The chip realizes stable frequency lock function in steady state and fast response in transient state.The work of this article has completed the layout design of the chip and postsimulation verification. |
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