A 12 Bit Ultra Low Power SAR ADC For Bioelectrical Signal Detection Circuit

Due to the enhanced awareness of personal health, wearable smart device and portable medical equipment obtain rapid development. In order to provide reliable realtime monitoring of health, we need to quantify the human body’s biological electrical signal constantly, and sent the data to the DSP core for further processing. As the core module of ultra low power analog front-end, the power consumption of ADC need to be reduced as much as possible without performance taking a hit. The frequency range of the bioelectrical signal is usually between 0 Hz-10 kHz, while the successive approximation analog-to-digital converter(SAR ADC) just has the advantages of low power consumption and high precision in this frequency range, and meets the requirements of wearable devices and portable medical devices for low voltage and the low power consumption. Then with 90 nm CMOS technology, a 12 bit ultra low power SAR ADC for bioelectrical signal detection circuit is proposed in this paper.Firstly, since the bioelectrical signal and sensor signal are usually characterized by small fluctuation in long time range, periodic changing, and the peak and valley of the signal easily distinguishing, an interval prediction algorithm is proposed in this paper. Due to the interval prediction technique, the quantization cycles of ADC can be reduced, which is a new breakthrough to further reduce the power consumption of SAR ADC.Secondly, the two phase outputs of DAC are not very close at all time in SAR ADC, which means that it is not always need a high accuracy comparator in each quantization cycle. Occasionally in one of the first few cycles and the last two cycles, a high accuracy comparator is needed. So we design a two mode comparator, different modes are selected for different situations. The power consumption of the comparator is reduced on the premise of performance guarantee.Thirdly, after sufficient Matlab modeling, a binary redundant split-array DAC structure based on the compensation capacitance is also proposed in this paper. During the high segment compare, a coarse comparator just can meet the requirements, and the lower segment compare use the fine comparator as usual. Because of the redundancy, comparison error caused by low accuracy mode in high segment can be corrected in the lower few cycles.In addition, there are also some low power techniques used in this paper include vcm-based DAC structure, low supply voltage, transistor stack, time sequential logic optimization etc.Finally, simulation results based on Hspice show that under the sampling frequency of 250 kS/s, the ADC achieved an SFDR of 81.6 dB, an SNDR of 72.8 dB, an ENOB of 11.80 bit. The total power consumption is 8.981 μW, thus resulting in an energy efficiency of 10.07 fJ/Conv.-s.