Research On Memory Fault-tolerant Method Based On Data Correlation

With the rapid development of information technology,the importance of data storage has become increasingly prominent.Due to the continuous progress of integrated circuit technology,the size of memory cells in storage becomes smaller and smaller,and the density of storage units increases.The data stored are more susceptible to errors due to electromagnetic interference,radiation and so on,which is likely to have a serious impact on production and life.There are two main types of existing memory fault-tolerant protection methods,one is hardware fault-tolerant technology and the other is software fault-tolerant technology.The part of the hardware fault-tolerant technology that involves the circuit process and manufacturing has the disadvantages of high cost,high consumption of hardware resources,and poor portability.Compared with hardware fault-tolerant technology,software fault-tolerant technology can be well reflected in the advantages of low resource consumption,no special requirements on hardware,and strong portability.Therefore,it is very important to conduct protection research on memory based on software fault-tolerant technology.Firstly,from the perspective of software fault-tolerant technology,this paper proposes a new method for multi-bit error location and error correction in memory based on the correlation between data.Secondly,this paper makes a detailed theoretical analysis of the fault-tolerant protection method,and according to the characteristics of the fault-tolerant method,it divides the basic error types.Moreover,the error detection and location and error correction methods of the fault-tolerant protection method are described in detail respectively.For the case of more errors,the fault-tolerant method combined with the loop iteration error correction method is proposed to correct more errors.Then,the implementation and debugging of the fault-tolerant algorithm in this paper is completed by C language,and the complexity analysis of the algorithm is carried out.Then,based on the DW8051 core and DE2-115 FPGA experiment board,the hardware platform of the fault-tolerant system is completed by adding the three parts of the flag signal output module,SRAM interface module and serial port upload module.The flag signal output module is used for communication between the hardware platform and the error-injecting device,the SRAM interface module is used for connecting the memory and the hardware platform,and the serial port uploading module is used for uploading the detected error information.Finally,the fault-tolerant system and the heavy ion error-injection experiment based on the fault-tolerant method of this paper are respectively carried out,and the FPGA-based board level verification of the method is successfully completed,and the experimental results are summarized and analyzed.Moreover,the performance of the fault-tolerant method is compared with the existing mainstream error correction code in terms of error correction capability and complexity.Based on the data-correlation memory fault-tolerant method,this paper can quickly and accurately locate and correct multiple bit errors,which has low algorithm complexity,and its consumption of hardware resources will decrease with the increase of data volume.And it is possible to locate and correct these errors in the event of a serious error in the memory.The results of random error-injection experiments and heavy ion error-injection experiments show that the fault-tolerant method can correctly correct any-bit errors when the error is a basic error type.Compared with the BCH code and the RS code,the fault-tolerant method reduces the execution time by an order of magnitude when dealing with the same amount of data,which proves that the method has certain practical application value.