Research On Fault Tolerant Hardware Cryptographic Algorithms

As Embedded encrytpion chip is an important carrier for encryption algorithms,which is under attacks from both theoretical level and physical implementation level.Although data is encrypted during the co mmunication,this still cannot guarantee its correctness and reliability.How to detect and correct this fault attacks by the attacker becomes one of the challenging research topics.In this research work,we focuse on the Advanced Encryption Standard(AES)algorithm;after we analyze the fault-tolerant scheme for AES,we draw the conclusion that the existing methods have the drawbacks of larger area,low rate of error correction and inflexibility.To solve these problems,we propose two improved methods in this research work:The first method is fault detection scheme for AES over GF(24)field.In this method,we optimize fault detection for S-box over GF(24)field,which is the most area consuming module in the AES implementation.The scheme implements simply,applicates flexibly and effectively reduces the hardware area of fault detection for S-box.Detailed designs of the proposed S-box and AES are described in this paper.The second method is AES fault-tolerant countermeasure based Reed-Solomon Codes,which combines the operating modes of AES.In this method,the design uses a widely used error correction code technology-RS codes for the AES encrypted data channel encoding;the scheme effectively ensures the accuracy and reliability of data transmission,which has strong abilities of error correction and anti-interference performance.And we describe the designs of the operating modes of AES and RS encoding module.In the end,we port the above two designs to FPGA platforms.The experimental results show that fault detection for AES over GF(24)field scheme has the advantages of smaller area and lower cost;AES fault-tolerant method based RS codes has the advantages of high rate of error correction,high reliability and high safety without increasing larger hardware resources.