Study And FPGA Implementation Of GPS Signal Parallel Acquisition Based On FFT Algorithm

This thesis researches on the parallel acquisition algorithm of GPS software receivers based on FFT algorithm and elaborates its implementations using FPGA. Compared to the other acquisition projects, the project proposed in this thesis satisfies the real-time signal processing better.The main part of this paper involves four aspects. Firstly, it analyzes the basic principles of spread spectrum communication, and introduces the composition of GPS system and the characteristics of the GPS signal. In this part, constitute framework of GPS receiver is designed according to composition of GPS signal. Secondly, through studying on the kinds of acquisition schemes of GPS receiver deeply, the parallel acquisition scheme based on FFT is designed, which is faster and simpler, and its improvement measures are proposed. According to preceding analysis, farther system project is refined, and simulates the project using MATLAB. The simulation results of the system confirm the feasibility adequately. Thirdly, for the core part in the processing of acquisition—FFT processor, this paper realizes FFT processor based on FPGA but using the IP core provided by ALTERA. Comparing a group of simulation data obtained by the project proposed in this paper with the output of FPGA, the correctness of the FFT processor is confirmed. In succession, the FPGA realization is analysis particularly, which is one part of the parallel acquisition in the GPS receiver. Waveform of the FPGA timing simulation shows that the system has been able to realize acquisition of GPS signal successfully. Finally, it summarizes the whole work of this paper and proposes the direction of future research.This paper studies on the GPS receiver, whose principles are so similar to GALILEO, Beidou navigation system receiver that it is able to play a positive role in promoting our satellite navigation enterprise.