Research And Implementation Of Real-time Image Magnification And Rotation Based On FPGA

With the development of image processing technology and microelectronic technology,more and more image processing algorithms can be realized in real time in hardware systems.This paper aims to develop a system with high performance and expandable image rotation and image magnification.It starts from two aspects: algorithm improvement and hardware implementation.It rationally designs the hardware architecture and rigorously deduces the original image to the rotating magnification map.The coordinate points mapping relationship is an in-depth analysis of the cause of image degradation in the interpolation process,and an image sharpening strategy for the FPGA platform is proposed.Through the parallel design of the algorithm and hardware platform optimization,the system achieves a maximum processing speed of 100 fps at 640×512 resolution with four times zooming and rotating image.The main work in this paper is summarized as follows.(1)Algorithm designing.Image rotation and image enlargement are basic operations in the field of digital image processing.In the hardware implementation of the algorithm,due to the limitation of hardware resources and real-time requirements,the selection of interpolation strategy in image rotation is too simple,and the image quality needs to be improved.In this paper,the algorithm combining image rotation and enlargement is proposed,which is divided into two parts: coordinate mapping and sub-pixel interpolation.In the coordinate points mapping,the coordinate relationship between the original image and the enlarged image coordinate,and the coordinate relationship between the enlarged image and the rotated image is obtained,Simplifying the algorithm flow while implementing two functions,this paper directly building connection from the original image to the rotated enlarged image.In the process of sub-pixel interpolation,based on the blurring problem of reconstructed image caused by convolution of coefficient matrix in 4?4 template,a unidirectional enhancement template algorithm based on bicubic interpolation algorithm is designed.In the process of video stream data processing,using the single direction enhancement templates of 0 degree,45 degree,90 degree and 135 degree recycling to achieve the effect of sharpening enhancement in four directions due to the persistence of human vision.(2)System designing.Aiming at the multiple input and output sources faced by the image processing system,as well as the power consumption,extendibility and manufacture cycle of the system,this paper adopts the hardware system based on FPGA is used as core processor to realize the function of enlargement and rotation.In the process of hardware design,according to the modular design idea,the system architecture can be divided into three parts,including interface board,memory board and core board.TPS62130 power management chip is used to provide the power supply to each part of the system by configuring different resistors.By cascading power management chip,the power-on timing of the FPGA is ensured.Following the PCB layout and routing specifications strictly,the high-speed signal communication stability of DDR3 and eMMC is ensured.(3)Parallel designing of algorithm.The algorithm is designed parallel aimed at the characteristics of the FPGA platform.According to the design flow of the algorithm in this paper,the module of coordinate and image convolution needs to observe the principle of speed-area interchange and handing skill of pipeline and ping-pong operation.At the same time,considering the difficulty of FPGA floating-point arithmetic,the trigonometric function values and interpolation templates involved in the algorithm are enlarged and implemented in the form of ROM look-up table to ensure the calculation accuracy and improve the processing speed of the system.By setting access priority of data stream reasonably in the DDR3 arbitration module,the algorithm can run stably and efficiently.(4)System optimizing.In the process of hardware implementation of the algorithm,the main factors limiting the system technical parameters are the amount of resources of the FPGA and the communication bandwidth between the FPGA and DDR3.In order to maximize the application of FPGA resources,the algorithm performs block operation and multi-block simultaneous processing design,and the area is changed in speed to improve the system processing capability.At the same time,through deeply exploring DDR3 physical control timing,optimizing DDR3 IP control logic,and adopting multi-BANK non-newline smooth writing,this paper achieve the purpose of releasing communication bandwidth of the bus effectively and improves the processing speed of the system.