The UVM-based Verification Of The CLB In FPGA

FPGA is widely used in the integrated circuits,there are many advantages of the full-custom-designed FPGA for example it can reduce circuit power consumption and the size of chip etc.The complexity of the full-custom-designed FPGA grows rapidly with the circuit design scale reaching tens of millions,thus the verification of full-custom-designed FPGA is getting harder and harder.Full-custom design and high configuration can not be considered by normal verification methods,meanwhile it takes too long by using the spice simulation.My research focus on the CLB of the full-custom-designed FPGA.By considering the full-custom-designed circuits and high configuration circuits,we achieve a verification process of the CLB,which is complete,precise and effective.The verification process consists of the preparation of the DUT,the design of the verification platform and the execution of verification.As for the preparation of the DUT,we study the CLB circuits and analyze the configuration and functional implementation of CLB.By analyzing the circuit with loop and using the behavioral level description to build the functional model for basic unit module,we complete the Verilog of the full custom design.Then,we make the equivalence check to insure the functional model is same as the original design.After that,we translate the netlist files to the DUT.Resolve the problem that the full-custom-design can not be verified by UVM.Then we extract function points,design a verification scheme for the DUT,determine the difficulty of verification,and propose a solution to the verification for full-custom-circuit.As for the design of the verification platform,we build the verification platform by using UVM and design environment components.We especially focus on high configuration in the design of driver,monitor,scoreboard and etc.,distinguish each data transmission and results comparison of every function by use the transaction with task,simultaneously print correct comparison information and error submission information,visually reflect the transaction information from scoreboard and monitor,realize the automated operation of the entire platform.Then we design the functional coverage component and configuration coverage component,guaranteeing completeness of verification.As for execution of verification,we achieve an one-click operation platform by design custom scripts.At last collect verification results for testing,confirm the correctness of the verification method,According to the automatic comparison and coverage component,by adding directional test incentives,the functional coverage reaches 100% and configuration point coverage reaches 95.31% are observed,which meet engineering requirements.Finally,the CLB module is verified efficiently,meeting the needs of automation and timeliness.In the post-engineering practice,the verification platform of CLB in MPW is realized by vertical multiplexing of the platform,which greatly improve engineering efficiency and reduce the workload of the verifier.The research results of this paper provide solutions to the verification of large-scale full-custom-circuits in practical engineering.