The Design And Implementation Of Convolutional Neural Network Based On FPGA

As one of the representative algorithms of artificial intelligence,convolutional neural network(CNN)is a typical multi-layer neural network.Its sparse connection and weight sharing are the cornerstones of subsequent artificial neural network research,has a milestone in the field of artificial intelligence.CNN has important application value in image recognition,image processing,speech recognition,video processing and other fields.At present,CNN's implementation platforms mainly include CPU,GPU,ASIC and FPGA,in which CPU can not play the parallelism of CNN algorithm,GPU power consumption is too high,ASIC flexibility is poor,and development cycle is long,but in the future the application side,95% of applications are in the direction of artificial neural network inference process,so research people will focus more on low-power,low-latency,programmable FPGAs.FPGAs are rich in logic resources.By writing internal structures,large-scale parallel computing can be realized,and the characteristics of CNN parallel computing can be fully utilized.This paper proposed a method based on FPGA technology to achieve high parallelism,recognition performance and recognition rate of CNN.Experiments show that this method reduces the time consumption by 43.8% compared with CPU,and the operation speed is 19.5% higher than that of GPU.This paper first introduces the research status of convolutional neural networks at home and abroad and the types of convolutional neural network implementation platforms,analyzes the advantages and disadvantages of various hardware implementation platforms,and elaborates the hardware mainstream direction and main research techniques of AI hardware acceleration direction.In the second chapter,the algorithm flow of convolutional neural network is introduced in detail,including two-dimensional convolution calculation,pooled sampling,activation function,back propagation training weight,neuron full connection and classifier calculation.In the third chapter,we proposed the overall design scheme of hardware architecture.The network model structure and training parameters are introduced in detail,and the specific hardware network architecture,including controller,input/output memory and processing units,is designed for the network.The parallelism that can be realized in the convolutional neural network is analyzed in detail.The parallelization implementation strategy of the hardware network reduces the time consumption in the hardware calculation process.In the fourth chapter,the implementation process of convolutional neural network based on FPGA is introduced in detail.The difficulty and implementation process of data alignment output in convolution module and pooled sampling module in hardware architecture are analyzed in detail.We proposed the data secondary cache strategy based on SUP_address,which improves the correctness of hardware calculation accuracy and reduces the time consumption of the next layer of data preprocessing.Finally,the fifth chapter shows the simulation and test results of the design system.The designed system was tested on the software side using the MNIST handwritten digit set to verify the reliability of the system;the total module and each sub-module of the system are tested on the hardware side to verify the correctness of the system module and the accuracy of calculation and storage of the sub-module;finally,the same network model is used to identify pictures on the CPU,GPU and FPGA platforms,and the recognition speed of each platform is compared,which shows the advantage of FPGA in computing power in convolutional neural networks.