Accelerated Design Of Composite Convolutional Neural Network Algorithm Based On FPGA

Vision is an important means for humans to obtain external information.For patients with pathological changes or lesions,the blind assist system can effectively help them to see the light and complete some of the visual tasks in daily life.With the application of new technologies such as convolutional neural networks,the functions and new capabilities of blind assisted systems have been further enhanced,and the help provided by blind people is becoming more and more abundant.However,new technologies such as deep learNINg require huge computational consumption in the application process and need to be deployed in server-side or high-performance computers.This makes convolutional neural networks difficult to implement in lightweight platforms for blind assistive systems,so FPGA platforms are the convolutional neural network under the model has a very important significance for the design of the model and circuit.Based on the GoogLeNet model and the SqueezeNet modely this paper proposes an improved parallel Inception algorithm model from the perspective of hardware implementation for the low parallelism and poor water flow efficiency of the original model in the FPGA platform.Through the analysis of GoogLeNet model and SqueezeNet model,the data flow calculation process of Inception algorithm is adjusted and re-cutted to obtain a high-accuracy neural network model suitable for FPGA platform deployment.Compared with other classic lightweight network models such as RCNN-A2 model,Maxout model,DSN model and other standard CIFAR datasets,the experimental results show that the improved Inception model achieves an accuracy of 90.04%compared with the Maxout model.The high accuracy rate is 2.62%,which is 2.13%higher than the P ReLU model and 0.63%higher than the DSN model.It is close to the accuracy of the RCNN-A2 model,showing high recognition accuracy and robustness in complex scenarios.At the same time,it has better hardware affinity with other convolutional neural networks,and has a higher acceleration advantage in the FPGA implementation of convolutional neural networks.This paper completed the FPGA hardware implementation of the parallel Inception model.By using instruction control and multi-state calculation,the network model is deployed in the FPGA to realize the loop operation of the network.The Vivado Simulation simulation tool was used to simulate each functional module,and then the corresponding hardware test platform was built on the ZCU-120 development board to verify the function of the model.In this paper,the pre-edited test vector is input into the calculation module of the algorithm by means of serial communication.The data of the Key node is captured by Xilinx's own online logic analyzer,and compared with the calculation result of TensorFlow.The final hardware test results show that the parallel Inception model proposed in this paper has significant hardware acceleration performance and robustness.The calculation effect is the same as the software calculation.The peak processing speed of 663 FPS is obtained under the system clock of 200MHz.