A Research And Implementation Of Digital Direct Synthesizer Based On Residue Number System

Direct Digital Synthesizer(DDS) plays a key role in modern electronic systems. DDS is so significant which is regarded as the heart of many electronic systems. However, large scale hardware is required to generate high performance waveform based on conventional architectures. In practice, only a few most significant bits(MSBs) of phase accumulator output are used as the address of Look-Up Table(LUT) in general DDS designing. The truncated phase information results in phase error. Phase error becomes the primary factor of Spurious Free Dynamic Range(SFDR) performance of generated waveform. In order to reduce the hardware consumption or improve the waveform performance equivalently, Residue Number System(RNS) and Algebraic Integer Quantization(AIQ) is applied to optimize the DDS architecture in this dissertation.Firstly, in order to reduce the size of LUT and improve the speed of phase accumulator, the output of phase accumulator is converted to RNS representation. As result, the LUT depth is reduced from N to drastically. Meanwhile, the critical path of phase accumulator is also shorten. Nevertheless, it is achieved at the expense of additional multiply-add operations for the outputs of LUTs. For purpose of improving these multiply-add operations performance, the samples in LUTs is also converted to RNS representation. Although additional operations are required in the RNS based DDS architecture, better performance in area and speed can be obtained when Signal to Noise Ratio(SNR) or SFDR of the output waveform is very high.Furthermore, AIQ is also applied in this dissertation to improve the accuracy of multiply-add operations and the precision of samples in LUTs. In AIQ, a real number is representated by several small integers, what’s more the multiply-add operations of real number is replaced by that of those small integers. Thus, the precision is lossless in computation procedure. On the other hand, the addition for AI is performed in several independent channels, which results in high speed processing. However, the multiplication is more complex. For this problem, RNS and AI are combined in this dissertation to make both the addition and multiplication operations parallel and independent.In this dissertation, the algotithm, structure, implementation and performance analysis of RNS-based and RNS-AI-based DDS are performed. Simulation and ASIC implementation results show that the proposed architecture can achieve high performance in area and speed when SFDR of the output waveform is high. For instance, the implementation area of proposed DDS based on two channels RNS with phase truncation is only 6% of that of conventional DDS when the frequency resolution is 1/232,the bit width of output is 16 bit and the SFDR of output waveform is about 108 d B. Besides, the latency performance of proposed DDS is also optimized.