Research And Implementation Of FPGA Hardware Based On RapidIO-based Communication Middleware

With the development of Software Defined Radio,General Purpose Processor are limited by processing capabilities and cannot meet the needs of current radio communication services.More and more applications rely on dedicated processors such as FPGAs and DSPs to complete high-speed data processing tasks,and at the same time use the dynamic expansion capabilities of communication middleware to solve the problem of coupling of heterogeneous systems.However,the communication middleware connecting different types of processors in the system only exists as software,which becomes the biggest problem in the integration of FPGAs into the system;in addition,most of the contemporary tactical systems use embedded devices based on TCP/IP.Communication can no longer meet the needs of embedded devices for high-speed transmission,especially between chips and between boards.In this context,this thesis proposes to use the FPGA technology to hardwareize the communication middleware to solve the above problems.On the other hand,in order to solve the problem of the transmission speed of the communication middleware,this thesis replace the Ethernet communication with RapidIO communicationThis thesis first introduced the related technologies and platforms,then analyzed the design requirements of the publish/subscribe data communication model in the middleware.Based on this,this thesis divided the internal functional modules of the communication middleware,and studied and designed the overall architecture of communication middleware on FPGA and the hierarchical relationship between the various modules of the communication middleware within the FPGA.After that,according to the requirements of the application components on data communication and control,the data interaction format between each module is designed,and the data interaction relationship between various modules during the operation process of the application components is formulated.Thesis completed the design and implementation of data exchange control IP cores and equipment information management IP cores,and designed the processing flow of state machines and application component request operations within the IP core;The application component interface signals were defined in detail.And The operation timings of different types of interfaces are designed to meet the requirements of application components for theme configuration and data transmission.Finally,with the help of the PowerPC master node,the FPGA slave middleware node is tested and verified.