Research On Optimization Design Of SIFT Based On SOPC

The research of spatial vision in computer vision has been a hot research field in recent years,and the image matching technology is the key of computer vision to the spatial cognition in the real environment.In order to ensure the correctness of image matching in the same scene in real environment due to complicated and diverse changes of light and sensor position and light sensitivity,the image matching algorithm based on local invariant features of images has achieved very good results.SIFT feature is known as one of the best features for the superior performance in image local invariant features.However,its algorithm is complex and computationally intensive,which makes it difficult to meet the requirements of large-scale image matching or real-time applications,such as real-time video stitching and Large-scale three-dimensional reconstruction.In order to solve the problem of time-consuming and inefficient short-board of applications based on SIFT algorithm for image matching,this paper proposes a SIFT feature extraction,description and matching acceleration solution based on SoPC platform.This dissertation starts with the optimization of SIFT algorithm based on digital logic design.By using the structure of SoPC platform ARM + FPGA,the control part of complex SIFT algorithm is realized on the ARM side,while the high computation part is accelerated by FPGA side.The work of this paper includes:(1)Based on the FPGA features,make appropriate adjustments and optimization of the steps of the SIFT algorithm.In the feature extraction section,a parallel scheme of SIFT scale space based on FPGA and the fixed-point and structure optimization design of Gaussian filter are proposed,which can accelerate the feature extraction while satisfying the continuity of scale.In the feature description section,the realization of the descriptor generation by digital logic avoids the rotation of local image under the premise of rotation and scale invariance.In the feature matching,the optimal design scheme using the structure of time parallel and space parallel to extremely improve the real-time image matching system.(2)According to the structural characteristics of SoPC platform,the algorithm process control and data interaction is implemented on the ARM side,which can flexibly coordinate the generation and matching of SIFT features of the system in parallel and greatly improve the computational efficiency and real-time performance of the system.(3)Based on the optimized SIFT algorithm,each function module designed and implemented on the FPGA side focuses on improving computational efficiency and saving hardware resource consumption while ensuring the features of algorithm rotation and scale invariance.The design of digital logic based on pipeline design,such as Gaussian line filter,makes modules work at the same time without waiting.The digital logic design of modules based on spatial parallel,such as descriptor matching module,can directly increase computational efficiency multiple times;Proposed transposed FIR structure Gaussian line filter and the design of the neighborhood window module can save nearly half of the hardware resources than the ordinary structure.According to the characteristics of SIFT algorithms and real scene of the system test,the size of two 640 × 512 image matching,to meet the rotation and scale invariance and projection transformation and lighting with good robustness at the same time,Only about 30 ms to get matching results,fully meet the needs of real-time image matching applications.