Research On Power-Aware Compile Optimizations Of Multithreaded Architectures

In recent progress of microprocessor technology -- e.g. the rapid increase of the clock frequency and chip complexity, as well as its wide use in mobile systems– power consumption is becoming a key problem in hardware and software design. In addition to optimize system efficiency, compiler designers must also face the challenges of minimizing the power consumption while not reducing the system performance. This subject has attracted recent attentions, and has a great potential where pure circuit techniques alone is difficult to explore. Although still a new research field, compiler power optimization has opened a rich area for research. This dissertation will be focused on the compilation Techniques for multithreaded architectures where dynamic power/frequency scaling can be applied. In particular, main contributions of this dissertation include:(1) Proposed a classification of multithreaded architectures with hardware support in terms of low power compiler optimization techniques. Based on their architecture characteristics, we divide...