Research Of Image Sensor Readout Circuit Based On Visual Prosthesis

Visual prostheses can restore the vision of blind patients.The visual prosthesis uses the image sensor to sample external image information and process it,and then stimulates the optic neurons with the microelectrode array implanted in the body,there by generating artificial visual perception in the visual center.Image sensors are an indispensable part of visual prostheses.This paper mainly studies and designs the readout circuits of two different architecture image sensors.In the first scheme,the Laplacian operator for edge detection is implemented locally in the pixel unit,thereby implementing pixel-level parallel processing of the picture.A single pixel unit includes a photodiode,a convolution operation module,a current control oscillator module,and a pulse control module.Based on the SMIC 0.18?m process,the Spectre tool was used to design and simulate the circuit under the Virtuoso platform.The layout area of a single pixel is 45?m×45?m,and the area of the entire 64x64 array is about 3mmx3mm.Simulation shows that the scheme can effectively perform edge extraction for lower pixel images.In the second scheme,after the photoelectric signal is converted into a digital signal,the digital module performs image processing.The readout circuit consists of the correlated double sampling circuit,the programmable gain amplifier(PGA),and an analog-to-digital converter(ADC).According to the characteristics of the pixel unit,3T-APS is used to achieve a high fill factor.At the same time,the correlated double sampling circuit is used to eliminate fixed pattern noise(FPN).The PGA uses a two-stage pipeline structure with a one hot code and a thermometer code to reduce power consumption and enhance the loop stability,the ADC uses MSB capacitor split structure and reduces the switching power consumption of the capacitor array through specific capacitor switching timing.Based on the SMIC 0.18?m process,the Spectre tool is used to design and simulate each module under the Virtusuo platform.Simulation shows that the gain range of the PGA is OdB to 15dB,the gain error is less than 1mV,the SNR of the ADC is 60.85dB,and the SFDR is 63.65dB.The ENOB is 9.64bit,and the FOM is 151.4fJ/step.The dynamic power consumption of the ADC is 13 AC VREF2 calculated by MATLAB.The power consumption is reduced by 99.020%compared with the traditional switching timing,and the area is reduced by 75%.Finally,the joint simulation of the entire readout circuit proves that the function of readout circuit is correct.