Research And Verification On Key Techniques Of Rate-compatible LDPC Enoding And Decoding

LDPC codes have been widely used in diverse communication systems due to their excellent error correction performance.In general,parity-check matrices of LDPC codes are immutable,which makes the code length and rate of LDPC codes constant.Therefore,conventional LDPC encoders and decoders are lack of flexibility while rate-compatible coding schemes are required.Both puncturing scheme and parity-check matrix reconfiguration are independent approaches to change the code length and rate of LDPC codes.Based on the existing LDPC codes in IEEE 802.11 ac standard,a new rate-compatible LDPC(codes whose name is rate-changeable LDPC)encoding and decoding scheme,is constructed by combining ‘grouping and sorting' puncturing procedure and parity-check matrix reconfiguration.Ensuring high throughput and error correction performance,rate-changeable LDPC codec provide low implementation complexity,and both of them could reduce nearly one half comsuptions of FPGA computing resources while comparing with single-rate codec.The main contents are as follows:First,the definition of channel coding theory is introduced.As one of the most significant channel coding scheme,some basic concepts and matrix expressions of LDPC codes are described in detail in this paper,including degree distribution,generator matrix,parity-check matrix and Tanner graph.Then the research status of rate-compatible LDPC coding is analyzed in this paper,including the definition of three main methods of changing coding rate,such as puncturing,shortening and extending,respectively.Puncturing algorithms are mainly analyzed in this paper.Second,rate-compatible LDPC encoding and decoding scheme is introduced.This paper summarizes parity-check matrix encoding method and Min-sum probability propagation decoding algorithm,and then detailedly analyzed ACE message degree puncturing scheme and ‘Grouping and Sorting' puncturing procedure suitable for Quasi-Cyslic LDPC codes.Considering the complexity of implementation,the combination of parity-check matrix reconfiguration,normalized Min-sum decoding algorithm and ‘Grouping and Sorting' puncturing procedure is established to be the basic theory of rate-compatible LDPC codec in this paper.Third,the FPGA design of rate-compatible LDPC codec is described in detail.Firstly,all implementation flowcharts in the encoder and the decoder based on parity-check matrix encoding method,‘Grouping and Sorting' puncturing procedure and normalized Min-sum decoding algorithm are constructed respectively.Some inner submodule partitioning diagrams are also introduced.Finally this paper introduces feasible implementation scheme and overall verification results of rate-compatible LDPC codec in this paper.The implementation results have already shown that rate-compatible LDPC codec designed in this paper can support arbitrary continuous LDPC coding rate,and save about half of FPGA resources compared with independent multi-rate codec within few BER performance cost,which provides certain reference for IEEE 802.11 ac communication systems in their practical applications.