Research And Design Of Ultra-Low Power Wake-Up Receiver

In the Internet of Things era,the number of communication equipment increases explosively.With the formal freezing of the narrowband Internet of Things(NB-IOT)3GPP standard,the application scope of the Internet of Things will be more and more extensive,so as to achieve real connection of all things.In such a massive application demand background,low-cost,low-power and low-latency wireless communication has become a research hotspot.Since the concept of the Internet of Things was put forward by Professor Kevin Ash-ton in 1999,many scholars have been devoting themselves to the study of this aspect and have made great achievements.In 2007,Professor Jan Rabaey of the University of California,Berkeley,proposed a novel wake-up receiver technology.Traditional receivers have high power consumption and are difficult to be used in the Internet of Things environment.The common practice makes the receivers work at a certain duty cycle and switch between working mode and sleeping mode periodically,which leads to higher latency of the receivers.The wake-up receiver technology can solve this problem perfectly by placing a wake-up receiver beside the main receiver which receives data at very low power consumption.Usually,the main receiver is closed and the wake-up receiver is always on.When the wake-up receiver receives the communication requests,the main receiver starts to work.When the communication is comleted,the main receiver will be closed.This not only ensures the real-time communication,but also meets the low power requirements of the Internet of Things.This paper firstly describes the working principle of wake-up receiver,summarizes several architectures of traditional receiver and wake-up receiver,and makes detailed analysis and comparison.By investigating domestic and overseas literature about ultra-low power circuit,it is found that the power consumption in communication circuit mainly comes from the radio frequency circuit.Then this thesis summarizes some common methods to reduce the power consumption of radio frequency circuit and applies the methods to specific circuit design.The mixer circuit implements by using IBM 0.13 um CMOS technology.The working frequency of the mixer is 5.85-5.925 GHz and the core circuit part adopts the single-balance structure to reduce the power consumption.At the same time,the mixer introduces low-power design technology such as sub-threshold,to optimize conversion gain and noise figure in low bias current.After completing the layout design and extracting parasitic parameters,the results indicate that the frequency conversion gain of the mixer is 10.3dB;the double sideband noise figure is 13dB;and the power consumption of the whole circuit is only 0.26 mW.Ultra-low power wake-up receiver designs with GF 55 nmCMOS technology,and the working frequency is 700-960 MHz.The receiver chooses high sensitivity RF tuning structure,which consists of three parts: RF amplifier,envelope detector and comparator.In order to improve the dynamic range of the receiver,the RF amplifier is cascaded by multistage amplifiers and introducing switchs to form a gain adjustable structure.The envelope detector improves the traditional diode detector circuit and uses the common source structure to make the MOS transistor work in the sub-threshold region.This method reduces the conversion loss of the detector.The comparator amplifies the output signal to facilitate subsequent digital processing.With the help of Cadence software for layout design,considering the influence of parasitic parameters,the simulation results show that the sensitivity of the receiver is-65 dBm,and the DC power consumption is 50μW.