The Research On Erasure-in-Depth Technologies Of Floating Gate Transistors

With the development of integrated circuit technology,solid-state storage is widely used instead of disk storage.The floating gate transistor is a memory cell of Flash memories which is one of the representatives in solid-state storage.Data is stored in the form of charges in Flash memories.Due to the residual charges in the floating gate after erase or overwrite operation,data would be recovered by detecting threshold voltages or drain current,and in the meanwhile confidential information theft is brought about.Aiming at data remanence in floating gate transistor,the erasure-in-depth technologies are investigated,which is divided into two parts: modeling analysis and verification chip design.As to modeling analysis,based on TCAD tools,the process flow and working principle of floating gate transistors are analyzed,and the structure and basic operations of floating gate transistors are carried out.In order to further verify the feasibility of data recovery and provide the basis for the erasure-in-depth method,the threshold voltage analysis after erase is carried out by curve fitting method.It can be found that the threshold voltage difference between the last data 0 and 1 is at least about 1V.In order to eliminate this threshold voltage difference,the effect of the overwriting operation on the threshold voltage is studied based on the theoretical deduction and modeling analysis.Compared with overwriting two erase operations,the threshold voltage difference between the stored data 0 and 1 after the cell is programmed for previously erased is significantly smaller.Based on this,erase and program cycle sequence is proposed as a more efficient erase method.When the 5-times erase and program cycle operations are overwritten,the threshold voltage difference of the stored data 0 and 1 is at most 0.0001 V,which achieves the accuracy of the threshold voltage change caused by a floating gate electron.Through this method,the security of Flash memories is enhanced.In order to validate the data recovery problem caused by data remanence and provide experimental basis for erasure-in-depth method,the overall design of the verification chip is carried out.Based on the SMIC 0.18μm 5V Flash process,the circuit and layout design of the data recovery verification unit have been completed based on the difference between the last data 0 and 1.The simulation results show that the performance parameters could meet the design requirements well.