Research On The Convolution Neural Network Accelerator For Image Recognition

In recent years,convolutional neural network algorithm has made more and more outstanding achievements in the field of computer vision.The explosion of data today has made the algorithm "learn" more,and the powerful computing power provided by the development of integrated circuits has made the algorithm "learn" faster;however,while the algorithm is getting better,the complexity of the algorithm getting higher.On the other hand,smartphones,robotics,intelligent driving and other smart application are widely used,but because of the privacy and real-time requirements on these applications,the algorithm only can be operation locally.Today the traditional general-purpose processor architecture is not suitable for the algorithm,it is necessary to explore the acceleration of the algorithm to find a suitable hardware design method for accelerating the algorithm.1.In this paper,we have trained the face recognition algorithm based on convolution network,and then we built a face detect system according to the face recognition algorithm.The system test results show that the face recognition algorithm trained in this paper has certain practicality;In addition,we also trained a digital recognition algorithm based on convolutional neural network;both algorithms have achieved high recognition accuracy.2.In this paper,some design methods are proposed to design a convolutional neural network accelerator architecture to solve the problem that convolutional neural network algorithm is difficult to calculate in the traditional processors with real time.The architecture designed dedicated multiplyaccumulate calculation units to deal with the intensive multiply-accumulate calculations on the algorithm;In addition,according to data reusability on the algorithm,different cache-levels are designed to reuse data and reduce additional memory accesses;Besides,the computing unit is designed to be a parallel mode,and the computing architecture is designed to be a parallel configurable form to support different parallel computing methods of the algorithm;according to the convolutional neural network algorithm,there are many "0" involved in the operation,so we designed the multiplier to avoid "0" participat;what's more,when designing the architecture,the two-dimensional convolution is decomposed into one-dimensional convolution,which reduces the use of multipliers and made the accelerator superior in performance to the other same type accelerator.3.In this study,the hardware accelerator architecture is designed on a FPGA,and we use the accelerator to implements face recognition and digital recognition algorithm based on convolutional neural network.Experimental results show that the accelerator can recognize about 3,000 images per second,it achieves a speedup of up to 28 times compared to the current mainstream CPUs,at the same time,compared to the same type of accelerator,the design reduce resources about 47%.