Face Recognition Algorithm Design And FPGA Verification Based On Deep Seperable Convolution

As one of the most popular research directions in the field of machine vision,face recognition technology has high application value in the fields of mobile payment,intelligent security and smart city due to its advantages of safety,reliability and non-contact.With the development of convolutional neural network,the accuracy of face recognition algorithm has been greatly improved,which has surpassed the human level,and its application prospect is more extensive.However,compared with the traditional algorithm,the face recognition algorithm based on convolutional neural network has more parameters and computation,and it requires more hardware resources,which makes it difficult to deploy to mobile terminals.Therefore,it is of great practical significance to implement efficient and fast face recognition algorithm based on software and hardware co-design.In this thesis,a face recognition algorithm is designed based on deep separable convolution.The number of model parameters and the amount of calculation are reduced by half.By introducing quantization operation and using low precision value for calculation,the times of data access and bandwidth requirements are reduced.By optimizing the network structure and loss function,the model performance is improved without increasing the number of parameters.The model recognition accuracy is greatly improved by preprocessing the data set and adjusting the training strategy.In the design of the convolutional neural network accelerator,the convolutional computing module with high data reuse rate and high parallelism is designed by expanding the convolutional computation layer by layer and splitting it by line.The pipeline operation and dual caching mechanism are used to reduce the data access times and data transmission delay.Finally,FPGA verification system was designed,and control code was written on Zynq XC7Z035 chip to complete the validation of face recognition algorithm.In this thesis,the face recognition algorithm based on deep separable convolution has achieved the accuracy of 94.4% in the LFW data set and 95.5% in the face database in the self-made laboratory.When the clock frequency is 100 MHz,the effective computing capacity of the convolutional neural network accelerator based on FPGA platform can reach 52.9 GOPS,and the performance power consumption ratio is 10.3 GOPS/W.When the face image size is 160*160,the recognition speed of the algorithm can reach25 FPS on the FPGA verification platform.The research of this thesis has certain reference value for the mobile terminal realization of high accuracy real-time face recognition system in the future.