Research On Deep Neural Network Accelerator For Low-cost FPGA

In recent years,deep learning technology based on neural networks has become a current research hotspot.However,while the performance of neural network is improved,its complex structure restricts the development potential of neural network in terminal application scenarios.Low-bit DNN is a new branch of neural network development,which has the advantages of low computational intensity and small storage requirements.Low-cost FPGA is one of the main hardware platforms to achieve DNN acceleration,and has the advantages of high flexibility and short development cycle.Therefore,low-bit DNN and low-cost FPGA provide a good solution for realizing high-performance DNN accelerator at the edge.However,the inherent mismatch between FPGA and low-bit DNN restricts the application potential of lowbit DNN on FPGA in actual deployment.This thesis is oriented to low-cost FPGAs and researches on the key technologies of low-bit DNN acceleration,which has important theoretical significance and practical value.The work of this thesis is summarized as follows:1.Aiming at the mismatch between FPGA and low-bit DNN,this thesis proposes a circuit architecture of BRAM and DSP co-processing.By taking advantage of the reusability of convolution parameters,the data buffer(BRAM)stores multiple low-bit data in a single address,and the DSP calculates the multiplication of multiple low-bit data in a single clock cycle.When calculating,the data only need to be read once from the data buffer,and multiple DSPs can simultaneously execute the convolution results of multiple filters and multiple input feature maps.It not only improves the computational efficiency of the DSP,but also reduces the number of data accesses,thereby improving the performance of the DNN accelerator.2.This thesis proposes a general data stream that can support multiple types of convolution calculations.When transferring data,the high-dimensional filters and the input feature maps are converted into two-dimensional data,which are arranged in order in multiple parallel data buffer(BRAM).In the convolution calculation,the output order of the data can be adjusted according to the convolution type to support the calculation of multiple types of convolution,thereby supporting the calculation of a variety of DNN models,and has strong versatility.3.This thesis implements a general-purpose DNN accelerator based on low-bit DNN for low-cost FPGA.Compared with the CPU running Mobile Net V2,the performance of the DNN accelerator proposed in this thesis has increased by 3.27 times;compared with the same type of DNN accelerator running Mobile Net V2,the DSP energy efficiency of DNN accelerator proposed in this thesis has improved by 12.8% and 109%.