Scalable And Energy-efficient Cnn Accelerator Design Based On Dynamic Accuracy

Convolutional Neural Network(CNN)is an important branch of deep learning.CNNs are widely used in computer vision,text processing,speech recognition and other fields.Due to the computational intensiveness of CNNs,traditional hardware acceleration solutions are difficult to meet the high performance and low power requirements of embedded devices for convolutional network computing.For the organizational characteristics of mixed structures in CNNs and satisfying the requirements of different computational precision,an energy-efficient convolutional neural network accelerator with dynamic identification,controllable precision and flexible extension is designed.Firstly,based on the complexity of input data,a multilevel CNN compression strategy based on dynamic recognition is proposed.The CNN can dynamically select the network layer to implement image recognition according to the input data.For the network structure level,the compression of the original network is achieved by means of convolution separation and channel separation;for the core operator level,the Winograd minimum filtering algorithm is used to reduce the number of multiplications of the convolution operation;For the operand level,compression of network parameters is achieved through a hybrid quantization scheme based on the convolution kernel gravity.For mainstream CNNs such as AlexNet,the computational complexity based on the strategy is reduced by 29.6%~40.5% compared with the original network.Secondly,according to the fault tolerance of the CNN,accurate controllable approximate calculation units are used instead of accurate calculation,and repeated multiplication operations are implemented by lookup tables based on one-write-multiple-read memory,so that the power consumption of multiplications is reduced by 37.5%~45.7%.In this work,The experimental results over a variety of benchmarks show that the energy efficiency of the proposed CNN accelerator achieves 1.92TOPS/W at 1.1V and 3.72TOPS/W at 0.9V in TSMC 45 nm process,which is 1.51~4.36× improvement compared with the state-of-the-art approaches.