Accuracy Controllable BCNN For Common Word Recognition Computational Structure And Implementation

Speech recognition is one of the important application scenarios of current deep neural networks.Speech wake-up technology is a keyword recognition technology that recognizes a small number of words and is an important branch of speech recognition technology.Its always-on characteristics make it extremely sensitive to hardware power consumption,so low-power hardware implementation in multiple scenarios is very important.The Deep Neural Network(DNN)has achieved great success in speech processing,but its huge parameters and calculations generate excessive power consumption.The Binary Convolutional Neural Network(BCNN)architecture with certain reliability and fewer parameters has become a new breakthrough in real-time low-power speech recognition,which can reduce a large amount of storage overhead and power consumption.This paper proposes a Keyword Spotting(KWS)system.In this paper,the algorithm and model of BCNN-based KWS system are analyzed.The feature extraction algorithm based on Mel Frequency Cepstrum Coefficient(MFCC)is selected and some specific algorithms are optimized.The system chose BCNN as the algorithm for the acoustic recognition model.Then the hardware implementation in the KWS system is introduced,include the feature extraction module and the speech classification module.The voice classification module is mainly a BCNN acceleration architecture.This accelerator contains a reconfigurable computing array.Based on the data reuse trajectory research of convolution operation,this paper provides a system for the reuse of convolutional neural network circular convolution calculation data for coarse-grained reconfigurable systems,which can accelerate the completion of large-volume convolution calculation and reduce the ressure of the bandwidth,and the convolution array is configurable.Finally,based on iterative logarithmic approximation multiplication,this paper designs the dynamic calculation precision and the approximate multiplication basic unit supporting multi-bit width calculation.The influence of different bit width error repair circuits on the calculation accuracy of approximate multiplier is analyzed.A two-level error calculation module is designed.According to different calculation accuracy requirements,the corresponding error calculation module is turned on or off by power-gating to achieve the function of controlling the calculation accuracy.This paper also uses the 4-bit×16-bit approximate multiplier as the approximate multiplication basic unit,which can be dynamic.The data bit width of the computing unit is reconfigured to accommodate different computational accuracy requirements.Energy consumption can be significantly reduced compared to standard computing units.The convolutional network accelerator scheme proposed in this paper has a power efficiency of 34TOPS/W when the voltage is 1.1V and the main frequency is 50 MHz under the TSMC 28 nm CMOS process.When the system selects 4bit data bit width calculation,the power consumption is as low as 0.6mW.Compared with the traditional accelerator scheme,the power consumption is reduced to 30%,and the recognition rate is as high as 94.7%,which is 5%.