The Design And Implementation Of DDFS Based On Quasi-linear Interpolation Algorithm

This thesis first introduces the basic principles and structures of DDFS and its components,and then analyzes several main methods of DDFS design.The proposed design replace the usage of ROM look-up table.The purpose of interpolation method is to replace ROM look-up table.The polynomial interpolation method is to approximate sine wave with polynomials,and get sine wave output through calculation,so as to realize the function of DDFS.The piece-wise polynomial equation is fitted by the MATLAB.According to the error between the fitting wave and the ideal sine wave,the approximate degree can be judged.Finally,the quasi-linear interpolation method combined with the linear interpolation and the parabolic interpolation is used in this thesis.The computational complexity of the linear interpolation method is lower than that of the parabolic interpolation method,and the accuracy is higher than that of the linear interpolation method.The proposed DDFS design consists of two parts: phase accumulator and phase-to-amplitude conversion block.Then the proposed DDFS is implemented on FPGA,and the circuit design consideration is combined with the resources of FPGA.In the circuit design of this thesis,the phase accumulator is realized by an adder and a register.As to the phase-to-amplitude conversion block,the square operation is realized by a multiplier,the multiplication operations are realized by adders and the shifter,and the coefficient selection is completed by the multiplexer.This thesis focus on the dynamic power of DDFS design.This thesis proposed an analysis method for dynamic power based on activity factor.Activity factor means the number of electrical level switching.By calculating the number of electrical level switching of the basic logic modules in the circuit,the number of switching activity of the whole circuit could be calculated according to the circuit structure.The larger switching number of the whole circuit,the more the corresponding dynamic power consumption will be.In order to verify if the proposed dynamic power analysis method is correct,and whether the proposed DDFS design method can reduce the power consumption.The DDFS proposed in this thesis is implemented on the platform of FPGA,measure the dynamic power consumption under different clock frequency,and compare the result with the dynamic power estimation results.It is found that thedynamic power consumption of the proposed DDFS design on FPGA is only 20% ~30%of the reference design under the same situation.The results show that the dynamic power analysis method that proposed in this thesis is correct,and the proposed DDFS power consumption is lower than that of other designs.According to the limitation of laboratory resources and the design requirements,the verification platform is the Xilinx Virtex-5 ML507 and the Altera Cyclone II development board,.On-line debugging is finished with Chipscope and Signal tap,and the output waveform of DDFS is observed with an oscilloscope.Finally,the proposed DDFS is taped out with 0.18 ?m TSMC CMOS process.The proposed DDFS has high frequency resolution: 0.023 Hz,high spectral purity,SFDR value reaching 96 dBc,consumes lower power,and the circuit structure is simple,easy to implement.