Digital Pll Frequency Synthesizer And Direct Digital Design And Implementation Based On FPGA

Frequency synthesizer is the core component of many electronic systems which has been widely used in modern electronic systems. At the same time, the performance of the frequency synthesizer is depended on many functions of this electronic equipment. Therefore, how to improve spectral purity, frequency conversion time, frequency resolution and other performance indicators of the frequency synthesizer has a highly practical significance and application value.Flying adder(FA) frequency synthesis belongs to the direct frequency synthesis which is different from the traditional DDFS. It needs multi-phase clock input rather than the single external reference clock; meanwhile the output is a square wave signal instead of sinusoidal signal which is the output of traditional DDFS. And FA is able to solve the frequency agility and high frequency resolution indicator problem.Firstly, this thesis introduces the basic concepts of frequency synthesis, key performance indicators and several commonly used frequency synthesis technology. Then the advantages and disadvantages of the typical technologies are analyzed which provides the theoretical groundwork for this thesis.Secondly, the flying adder and digital phase-locked loop models are given, meanwhile the function and principle of each module is analyzed. Then the relationships between the flying adder output waveform, frequency and the number of multi-phase clock, frequency control word and register bits are analyzed. Then two ways to combine flying adder and PLL are proposed. At the same time, the thesis uses Simulink to simulate the case that the flying adder is out of the phase-locked loop. By studying the characteristics of the output signal waveform and spectrum spurious under these circumstances combined with system simulation of the typical frequency control word, an approach which can solve the problem that the duty cycle of the square wave output is not constant is initially proposed.Finally, FAPLL is implemented by Verilog, meanwhile functional simulation and board-level testing are conducted and the square wave output signal with better spectral purity is gotten. Thus, this thesis prepares the way to create correct effective low spurious and phase noise of the wide frequency coverage mixed frequency synthesis for DDFS+FAPLL.