Design Of Direct Digital Frequency Synthesizer

In this paper, we shall introduce the structure, basic principle and ideal frequency spectrum of direct digital frequency synthesizer (DDS), and conclude some sources of output spurious signal in DDS: such as phase-truncation error, amplitude quantization error, digital to analog non-linearity error, clock leak error and switch transient error etc. Then in light of their properties, we adopt the method of time-domain waveform to analyze these influence generated by them in the output spectrum and provide the distribute pattern of their error frequency spectrum.In this work, after reviewing a lot of literatures published on DDS technology, a DDS scheme based on FPGAs'structure are proposed, and implemented in Altera's FLEX10K series FPGAs using MAX+PLUSII tool.The research including:1) Design of pipelining 32-bit frequency-phase accumulator with LFM(Linear Frequency Modulation);2) Design of phase-amplitude converter based on sin ROM Look Up Table;3) Introduce of various ROM register's compression methods in detail, and bring forward the improvement of ROM register's compression;4) Present several methods about how to reduce the spurious frequency in detail, and emphasize introduce the dithering measure;5) Implement emulator under MAX+PLUSII tool and use MATLAB language to carry out circuit emulator;6) Simply study Hybrid Frequency Synthesis: DDS+PLL.The experiment shows: used pipelining structures, modify the lowest bit of frequency-phase accumulator, phase dithering measure and look-up table compression etc methods, used FPGAs to realize DDS saved chip resources while satisfy the premise of functions.