Research On Key Techniques Of Fully-Digital Polar Transmitter For IoT Application

In recent years,the rapid development of Internet of Things(IoT)technology has promoted the related applications and services of the Internet of Things.In the future,the wireless network communication between IoT devices will increase rapidly,which poses requirements and challenges for wireless communication technologies.Faced by all mobile devices,low power consumption is also necessary for wireless communications.The proposed WIFI protocol of HaLow 802.11ah provides a good way for wireless transmission to solve this problem.Based on this,this thesis designs a low power digital polar transmitter,which is applied to wireless communication IoT devices.This thesis establishes a Simulink model for this polar transmitter and optimizes designs from the system and architecture level.In consideration of the trade-offs between resource utilization and power consumption,we design a architecture by continuously software simulation and complete the design from the algorithm to circuits layout.The effects of Cordic module,system quantization width,filter performance,and data sampling rate on transmitter performance are studied separately and the circuits are optimized based on this study.Finally,formal verification,static timing simulation,and post-simulation were performed to verify the correctness of digital circuit's function and timing.After the functional verification of the analog RF module,the layout level simulation was verified separately for each process corner.In order to improve the efficiency of the power amplifier,Class D mode PAs are used.The introduce of the switched-capacitor power amplifier array(SC-PA)and digital predistortion techniques are used to increase the linearity.The circuit design of the asynchronous clock domain saves a phase-locked loop for the system;the digital filter uses a half-band filter,which greatly reduces the hardware circuit;the polar domain modulation avoids the mismatch between I and Q signal;Gated clock and module reuse further reduce system power consumption.The transmitter architecture is entirely designed by digital circuits,which allows the system to benefit from improved process technology and the automated design of the circuit.The data transmission interface is completed by the JESD207 and SPI.The design of the all-digital polar transmitter was completed in the TSMC-65nm process.The total area of the chip is 1900x1200mm~2,which mainly includes four modules:JESD207,SPI,SC-DPA and digital polar modulation.Through co-simulation,the power consumption of the digital part in the 1 MHz bandwidth mode is 7.1 mW,and the power consumption in the 2 MHz and 8 MHz bandwidth modes are 14.4 mW and17.5 mW respectely.The total power consumption is 38.1 mW in the worst case.Under the DQPSK digital baseband signal,the worst EVM of the transmitter is 2.5%,the image signal suppression of the far-end spectrum can reach below-45dB,and the near-end spectrum complies with the spectrum MASK rules.