Silicon-based High Performance Digital Polar Phased-array Transmitter Design

To meet the requirements of modern wireless communication system with wide coverage,compact size,low power consumption,low cost,high data-rate,etc.,there are still some challenges and technique issues for silicon-based integrated phased-array transmitters,which are key constituent parts of the system.In this dissertation,silicon-based high performance digital polar phased-array transmitter and its key components,including wideband high performance passive circuits,wideband high efficiency digital power amplifier,feed-forward controlled digital polar transmitter,high resolution digital phase shifter,etc.,are investigated intensively.A series of novel architectures,theories and design techniques of the building block circuits are proposed,which are important in industry for practical application.Some techniques are applied in commercial chip and go to mass production.The research contents and innovations of this dissertation are concluded as follow:1.To improve the quality factor,insertion loss,operation bandwidth of the passive circuits in integrated radio frequency(RF)/microwave transmitters,some novel on-chip passive circuits with high performance are proposed.Firstly,stacked stepped-impedance transformer is proposed and analyzed.It is designed based on stepped-impedance inductor with high quality factor,and has better quality factor and coupling factor comparing to traditional uniform impedance transformer and planar-coupled transformer.It is suitable for the constituent part of the matching circuits in power amplifiers to improve the efficiency.Secondly,novel design method and theory of ultra-wideband balun with low amplitude/phase im-balance characteristics are proposed.The proposed balun adopts Marchand balun with stacked spiral coupled lines,self-coupled compensation line,center-tapped ground-shield,and deep trench structure,to improve amplitude/phase im-balance characteristics in ultra-wideband.A 6.5-28.5 GHz ultra-wideband balun is implemented using 0.13-?m SiGe BiCMOS technology.2.The design principle of Class-E wideband compact digital power amplifier is investigated.Based on the theory analyze of non-ideal wideband Class-E power amplifier,the design flow and theory guide of compact on-chip matching network for Class-E power amplifier is built.Based on the proposed stacked stepped-impedance transformer and digital amplifier array,a 3.5-9.5 GHz compact digital power amplifier is designed using 40-nm CMOS technology with drain efficiency of 46.2%.3.To improve the transmitter efficiency at saturated and back-off power,a novel architecture of feed-forward controlled dynamic matching digital modulated polar transmitter is proposed.The intelligent multi-mode judgement operation flow is given.The multi-mode impedance modulation technique is investigated.The dynamic impedance matching is realized with real-time controlling by baseband amplitude code and channel frequency.A 3.1-7 GHz fully integrated feed-forward controlled dynamic matching digital modulated polar transmitter is developed using 40-nm CMOS technology.The drain efficiency at saturated and 6-dB back-off power of the digital power amplifier in the transmitter is improved by 7.3% and 4.8% respectively,and the transmitter supports 64 QAM modulation signal with 136 Mb/s data-rate.4.Phase shifter is the key component in phased-array system.To develop phase shifters with high phase-shift resolution,low amplitude error,low power consumption,and compact size,the design method of digital phase shifter based on current limited vector-sum is proposed.It adopts reconfigurable variable gain amplifiers(VGAs)for vector modulation and quadrant selection,and the control algorithms of the VGAs can be optimized.Thus,the performance of the phase shifter,including amplitude error,phase error,power consumption,etc.,can be improved to fulfill requirements of different systems.This dissertation also derives the related equations between current limit factor and circuit components parameters,and quantitively analyzes the impact of non-ideal quadrature signals on the performance of vector-sum phase shifter,which can guide the phase shifter design clearly.A 3-7 GHz phase shifter is implemented by 40-nm CMOS technology,which exhibits root mean square(RMS)phase error of 0.41°,RMS amplitude error of 0.42 dB,and effective phase-shift resolution of 8-bit.5.A novel architecture of digital modulated polar phased-array transmitter is proposed.This architecture is based on phase modulation phase-shifting,which combines the advantages of local oscillator phase-shifting architecture,RF phase-shifting architecture,and digital polar transmitter architecture,respectively.Utilizing the characteristic of constant envelope of phase modulation signal,the impact of the phase shifter's implicit gain non-linearity on the transmitter's non-linearity is decreased significantly.The transmitter elements share many components,hence decreases circuits size and power consumption.With the characteristic of separated amplitude and phase paths in polar transmitter,the impact of phase shifter on transmitter's amplitude error is decreased.With high efficiency wideband digital power amplifier,high-resolution phase shifter,wideband compensated Marchand balun,feed-forward controlled dynamic matching technique,and quadrature phase modulator,etc.,the first 3-7 GHz digital modulated polar phased-array transmitter is designed with 40-nm CMOS technology.It achieves leading performances,including 9-bit effective phase-shift resolution,0.2 dB RMS amplitude error,and high system efficiency(38.2%).