Research On The Gate Metallization In NAND Flash

Nonvolatile memory market share has been continuously growing in the past few years,and further growth in the near future is foreseen,especially for NAND flash memories.As flash device dimensions get smaller and smaller,gate metallization in NAND flash has been identified to be one of the major limited factors,like nickel silicide?NiSi?for planar NAND flash and metal W for 3D NAND flash.The aim of this work is to give a deep study on gate metallization based on real process development issue in NAND flash memory.For planar NAND flash,low sorting yield has been observed in device with higher gate resistance which is due to poor gate metallization formation.Gate pre-clean process optimization is applied to increase the Ti silicide formation rate.Carbon injection into poly gate is adopted to avoid NiSi phase shift.Furthermore,in order to enlarge control gate profile window in NAND flash with small size tech node,a novel control gate process scheme using metal W is proposed.The process can reduce more than 300?control gate height compared to conventional poly NiSi silicide process.Easier profile control for gate word line will be achieved with high aspect ratio during processing.For 3D NAND flash,complex multi-layer stack peeling is serious issue due to 1^st gate layer W missing during gate etch back process.By introducing additional support contact,new process scheme could supply great support on multi-layer stack and avoid the peeling issue.The work presents a deep study of gate metallization issue for both planar and 3D NAND flash.Optimized solutions are verified by well-designed experiments and successfully applied in mass production.