Design And Implementation Of A Reconfigurable Architecture Simulator For Block Ciphers

With the continuous development of information technology,cryptographic chips play a crucial role in ensuring information security.Its application scenarios are ubiquitous.The use of a reconfigurable circuit provides both high performance and flexibility.The simulation model facilitates design evaluation in the early stages of hardware development.It is helpful in verifying the correctness of algorithm and hardware design in the later stage of hardware development.The reconfigurable cipher simulator designed in this thesis is based on the coarse-grained reconfigurable cryptoarchitecture model.Through the reconfigurable cryptosystem structure partition,the characteristics and commonality of the multiple block cipher algorithms are analyzed to design the basic operator units of the reconfigurable cipher array.A reconfigurable cryptographic array parameterization template is proposed.The reconfigurable cryptographic array can be changed by parameterized template,and simulator perform performance estimation to obtain the reconfigurable array parameters which meet the performance requirements of the algorithms.For the established reconfigurable cryptographic array,a cycle accurate simulator model is established to verify the algorithm configuration and perform software and hardware co-verification.It is necessary to perform reconfigurable cryptographic array area analysis before determining the array.By extracting reconfigurable cryptographic array area feature parameters,the thesis designs a reconfigurable cryptographic area prediction model based on neural network,which can accurately and quickly predict the area information of different reconfigurable password arrays.The reconfigurable architecture simulator for block ciphers designed in this thesis can simulate quickly,which is helpful to quickly verify and modify the algorithm configuration.The experimental results show that the simulation speed of the Non-cycle accurate simulator simulator is 842 times faster than that of the VCS,and the cycle accurate simulation model is cycle accurate without error;the simulation speed of the neural network area model is up to 3668 times compared with DC,and the maximum error does not exceed 4.16%.Through the above-mentioned simulator designed for block ciphers,the design and development cycle of reconfigurable cipher chips can be shortened.