Research On High Speed Visual Detection Of Linear Features Based On FPGA

In aerospace,space attack and defense,industrial pipeline and road traffic,there are a large number of high-speed moving targets.These targets have complex surface features,including various linear features,elliptical features and other irregular features.In order to achieve target location,linear feature parameters can be used to calculate the position and attitude of the target,so as to determine the location information of the target,while the current linear feature.Slow detection speed and high resource consumption have become a key problem restricting high-speed measurement.Therefore,high-speed visual detection of linear features of moving targets becomes the value of this paper.This paper aims at the high-speed detection of linear features.By optimizing the system structure,the high-speed detection of linear features is realized by hardware acceleration technology using visual detection method.Firstly,the hardware system is discussed.In the process of image transmission,CameraLink high-speed transmission interface is adopted to solve the problem of time-consuming in the process of image transmission.Then,the parallel computing problem of large data volume under high-resolution image is proposed based on the hardware processing unit of FPGA.Then the layout of the system algorithm is discussed,and the system-level task pipeline layout of the image preprocessing algorithm and the linear feature recognition algorithm is carried out.According to the advantages of parallel pipeline processing of the FPGA,the overlapping layout and the independent layout are integrated among the algorithms,which improves the processing efficiency of the system algorithm.Secondly,the structure of median filtering,edge extraction,threshold processing and edge thinning algorithm in image preprocessing is optimized,and the accelerated processing of the algorithm is realized based on FPGA,which realizes the function of processing multi-pixels simultaneously in a single clock.Finally,the edge pixels obtained by image preprocessing are used for line feature recognition.This paper analyses the main reasons that restrict the speed of line feature detection,and proposes a new method of line feature recognition based on FPGA.By improving the traditional Hough transform algorithm and utilizing the parallel processing characteristics of the FPGA,the Hough transform algorithm is implemented on the FPGA,and the calculation process of parameter coordinates is accelerated,and a local optimization system is proposed in the voting statistics stage.The processing algorithm reduces the system resource consumption under high resolution,and realizes high-speed visual detection of linear features.Finally,through the system experiment,the accuracy of line detection and the robustness of the system are verified,and the real-time performance and resource occupation of the system are analyzed.The experimental results show that the hardware acceleration technology can effectively improve the speed of line detection and has very high detection accuracy and robustness.Under the condition of high resolution of 2320×1726 and full frame rate of the camera,the real-time processing frame rate of the system reaches 193 fps,which has high real-time performance.Moreover,the optimization processing of the algorithm in this paper reduces the resource consumption of the system.It improves the efficiency of the system.