Design And Implementation Of High-Speed 3DES Encryption Chip Based On FPGA

With the development of information technology, and more and more extensive application of computer, network and information security problems are more prominent, gradually become a problem which can not being ignored, at the same time, information encryption as one of the most powerful weapon in information security, is playing an important role.DES (Data Encryption Standard) encryption algorithm as the encryption standard to today, is applied to a very wide range of areas. However, with the development of technology, it has been proven to be an unsafe algorithm. But the extension of the DES algorithm, namely, the emergence of 3DES algorithm, extremely makes up the unsafe deficiencies of DES algorithm. Using 3DES algorithm to replace DES algorithm could do less change for the original system, which not only improves the security of the system, and also can use existing resources to be reused to improve the efficient use of resources. With its powerful, less investment and development process, short cycle, confidentiality, and can be repeatedly modified and development intelligent tools, and so on features, FPGA becomes one of the preferred devices in the field of programmable logic device circuit design. Therefore, applied FPGA to design and implement 3DES algorithm has great practical significance and broad development prospects. This paper designes and implements an FPGA-based high-speed 3DES encryption system.In this paper, hardware design and implementation of 3DES encryption algorithm has been deep researched. To ensure the high speed of the system, in the base of analysis and study algorithms principle, combining the characteristics of DES/3DES encryption algorithm, using a fully pipelined design to improve the system clock frequency and throughput. According to this implementation, this paper presents series of design methods based on the 3DES encryption/decryption integrated circuit, including 3DES encryption chip architecture design and circuit design of each module method, and a detailed analysis of each sub-module bases on the characteristics of FPGA, which have solved the design problem of high-speed hardware implementation of the 3DES algorithm, and the system's overall encryption and decryption speed has been significantly improved.The design uses a hardware description language Verilog HDL for RTL-level code writing, and doing a comprehensive simulation by Altera's Quartus II 7.0 comprehensive tool based on Cyclone series FPGA chip EP3C40F780C6. The results show that the design meets the desired objectives.