Research And Implementation Of SAR Target Recognition Method Based On FPGA

With the development of deep learning,image recognition based on convolutional neural network has been widely used in SAR target recognition.Different from optical images,SAR image is discrete and variable,and its unique imaging mode is accompanied by the influence of speckle noise,which affects the image quality of SAR image and increases the difficulty of selecting features for target recognition of SAR image.Convolution neural network avoids the situation of manual feature extraction and has the advantage of active feature extraction from massive data,it improves the accuracy of target recognition and makes the recognition network suitable for more unknown data and complex scenes with its independent learning ability and fault-tolerant ability.The neural network has a lot of parameters and a complex network structure,which has a high requirement for the computing power of the processing platform.The traditional GPU processing has high computing power and fast processing speed,but the power consumption and cost are too high to meet some low-power application requirements.Therefore,deploying the neural network to the FPGA platform with high parallelism,low power consumption and programmable characteristics has become the current research focus.The thesis designs a SAR target recognition system based on neural network and FPGA.The main work is as follows:(1)In order to solve the problem that SAR image features can’t be extracted effectively manually,this thesis designs a SAR target recognition network based on Tensorflow,and uses convolution neural network to achieve SAR image feature extraction and SAR target classification.In order to make the network structure and parameters more consistent with the hardware structure,this thesis changes the network structure and reduces the amount of network parameters by using deep separable convolution;The network parameters are quantified in the way of post-training quantization,which reduces the data bit width and the volume of the network model.(2)In view of the high parallelism and low power consumption of the recognition network for the computing platform,this thesis designs and encapsulates the convolutional IP core,pooled IP core and fully connected IP core based on Vivado hls.The layout and wiring of the hardware network are carried out with the encapsulated IP core combined with the PYNQ core board,and the recognition network model at the hardware is realized.(3)Aiming at the application requirements of recognition network for high precision and high speed,this thesis designs a hardware-based network acceleration system.Through data path optimization,operation process optimization and Vivado hls instruction optimization,an integrated hardware acceleration research and design for SAR target recognition network is realized.Experiments and tests are conducted in a hardware and software collaborative manner,ensuring recognition accuracy while reducing system power consumption and improving recognition speed.