Hardware Design Of AES/3DES And Lattice Cryptosystem

The symmetric block encryption algorithms AES and 3DES all play an important role in many fields such as financial security,satellite communications,gateway servers,video transmission,mobile devices,virtual private networks,and wavelength division multiplex,ect.The most widely used CBC operating mode of these two algorithms limits the use of technologies such as the pipeline commonly used in the ECB mode to speed up the calculation because of the existence of the from head-to-end feedback loops.In the field of asymmetric encryption algorithms,a lattice cryptosystem based on the R-LWE difficult problem is the most competitive cryptosystem for resisting quantum attacks that takes both security and implementation efficiency into consideration.It is of great significance as a substitute for traditional algorithms such as RSA and ECC cryptography.Its key issue is its slower operation speed and greater hardware resource consumption.Multiplication on the polynomial ring is the bottleneck of improving throughput and reducing resource consumption.To solve these problems,this paper proposes different optimization designs for 3DES algorithm,AES algorithm and R-LWE-based encryption algorithm respectively,and correspondingly implements high-speed hardware implementation.The design of this article mainly includes:1.For the 3DES algorithm,since the functions on the critical path are all linear functions except the S-box,the two XOR gates of the junction of the adjacent two round functions are moved and merged into one XOR gate according to the exchange law of the linear function and the conjunction law of the XOR gate.Then,the pre-calculation changes the order of the S-boxes according to the key and XOR gates,thereby combining the XOR gate with the S box and maintaining the size of the S-box unchanged.By using the above methods,this article removes two XOR gates on the critical path of the 3DES algorithm,thereby improving the throughput rate.The throughput can reach up to 2.84 Gbps,1.69 Gbps and 1.07 Gbps under the SMIC 65 nm,0.13mm,0.18mm,respectively.The increase in area power consumption is not significant.Compared to previous work,performance has been greatly improved.2.For the AES algorithm,the Mix Column operation is combined with the S-box,and the T-box is obtained by precomputing the product of each byte of the S-box and the fixed value over a finite field.The T-box is implemented with a twisted BDD structure consisting of two parallel parts: a groups of 2:1 selectors and a 5:32 decoder.According to the key,the 2:1 selector group is changed and selected and the order of the bit-output of 5:32 decoder is exchanged.So the T-boxes are pre-computed to remove the XOR gates in Add Round Key on the critical path.The throughput can reach up to 12.4Gbps under the SMIC 0.13mm,which is higher than the previous related technical results.3.For R-LWE-based cryptographic algorithms,split the modulus into the additions or substractions of several powers of two,similar to the fast modularizing as NIST primes.The high-order value is transferred to the low position by the congruence operation,and the shifted addition or substraction is put together into different low position digits respectively.And then added or subtracted again until the result of the addition/subtraction is only one digit higher than the modulus value.At last,selectors are used.The 34-bit modulo operation(modulus is 7681)has a delay,area and power of 1.68 ns,5656?m2 and 3.9mw under the SMIC 0.13?m,respectively.Compared with previous work,the above results is much supior.